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Latest Articles on Electronic Design Automation (EDA)


Forum Post: RE: How can I express exponents like as 2^4 or pow(2, 4) in Ocean...

I got "2**i"

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My Life at Cadence: Emmanuelle Amouriaux

We have recently interviewed some of our EMEA team members to hear about their unique backgrounds and experiences shaping the future of technology with Cadence.  For our second interview, we spoke...

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BoardSurfers: Training Insights: Three Ways to Start OrbitIO System Planner

OrbitIO  System Planner is a multi-fabric interconnect planning and optimization solution. It provides a single-canvas environment where you can derive and evaluate connectivity between the dies and...

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BoardSurfers: Training Insights: Three Ways to Start OrbitIO System Planner

OrbitIO  System Planner is a multi-fabric interconnect planning and optimization solution. It provides a single-canvas environment where you can derive and evaluate connectivity between the dies and...

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bbspice fitting process taking too much time

Hi,I have an S parameter file generated by EMX for my oscillator. It has 56 ports and was simulated from DC-900GHz with a 1GHz step. When I used bbspice as the interpolation method for the nport, the...

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Forum Post: RE: Implementation of a LTSpice diode model in Cadence

Dear Andrew, A sincere thank you for "watching over my shoulder" and correcting my comment concerning the use of the ".scs" file extension for the PSPICE component netlist file. I, too, and continuing...

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IC Packagers: More Reasons to Move to 17.4 HotFix 013

As promised, we’re back with some more of the big improvements that are part of the QIR2 update release of 17.4 (HotFix 013). This time, everything is specific to our Allegro® Package Designer Plus...

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BoardSurfers: How to Add Fanouts Using Standard Via Structures

An increase in design complexity has forced designers to take novel approaches to meet routing challenges. Long back, designers used to group objects (vias, clines, or shapes) and copy-paste them in...

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BoardSurfers: How to Add Fanouts Using Standard Via Structures

An increase in design complexity has forced designers to take novel approaches to meet routing challenges. Long back, designers used to group objects (vias, clines, or shapes) and copy-paste them in...

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Event: SPIE

Attend the Advanced Lithography Digital Forum, the leading event for the lithography community and where leaders come to solve challenges in optical and EUV lithography, patterning technologies,...

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