Popular Articles on Electronic Design Automation (EDA)
VeSys 2.0 installation error
Some of my customers have experienced problems installing VeSys 2010_2a. When the installation is almost complete and VeSys manager is started the installation bombs out with the following message:...
View ArticleBoardSurfers: The New 17.4-2019 Dynamic Shape 'Fast' Mode is Truly Fast!
This year, it’s the new Fast shape mode, and I feel like I need to talk about it because it is a game-changer in working with positive shapes when it comes to performance and the display quality of...
View ArticleIC Packagers: An Introduction to Off-Grid Degassing
All of you doing advanced node package or silicon interposer substrate design in Allegro® Package Designer know what degassing is. And, while we talked last summer about massive performance...
View ArticleBoardSurfers: The New 17.4-2019 Dynamic Shape 'Fast' Mode is Truly Fast!
This year, it’s the new Fast shape mode, and I feel like I need to talk about it because it is a game-changer in working with positive shapes when it comes to performance and the display quality of...
View ArticleLoading a DxDesigner color scheme file
The attached script loads a DxDesigner color scheme (dxc) file and sets the object colors accordingly. The dxc file is an xml file with the format described in this tech note:...
View ArticleHow to use variables in Calibre DRC Check Map statement
Hi all, I am very new to Calibre DRC deck creation.For experimentation purposes, I wish to write the statement like this : DRC Check Map myrule GDSII "Smylayer" "$mydtype" "$outputfile" APPEND...
View ArticleNC-Verilog simulation error
I am new in using ncvlogI have an error when i am trying to simulate simple inverter |ncelab: *E,CUVMUR (./ihnl/cds0/netlist,19|10): instance '[email protected]_1<module>.PM0' of design unit...
View ArticleError when starting Momentum
Hi,I am trying to run Momentum from Virtuoso Layout suite. After creating the momentum view starting from the layout view of my cell, the setup screen where I set ports frequencies, etc., I hit the...
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Phase Noise Setup doesn't work in port/vsource
I'm simply simulating pss and pnoise for a port/vsource, with added phase noise "freq, noise(dBc)" pairs.In my testbench, there's only the vsource and it's labelled output, and gnd. In ade, I setup pss...
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Problem Simulating Noise Figure of Gm Cell (single Ended)
Hi,I was trying to simulate the NF of simple Inverter (Which I will use as a gm-cell at the output of my switch-cap passive mixer). Unfortunately I am getting NF=46.48 dB for my circuit.I have attached...
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