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Forum Post: Convert "xxxxxb#b" to "xxxxx"

: 0 : 0 August 14, 2019, 2:26 pm

Where "xxxxx" can be any sub string and "#" can be any number. However "#" would rarely be more than two digits. The two "b" characters that are converted to " " are always "b". An example input string...

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Forum Post: RE: ERROR: Netlister: unable to descend into any of the views...

: 0 : 0 May 14, 2017, 7:04 pm

Hi Andrew, This is the below error I have encountered while running ADE simulation. ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'spectre cmos_sch cmos.sch...

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Calibre LVS extraction with multiple fingers

: 0 : 0 May 23, 2016, 3:02 pm

Hello, I am using Cadence 6.1.6 with Mentor calibre v2015 3_37.23.I have a problem when I do the LVS test: in my schematic, I instancied a nmos transistor (width = 960nm with 3 fingers of 320nm each)....

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Forum Post: RE: How to read a text file in a VerilogA code

: 0 : 0 August 15, 2017, 12:16 am

Which simulator are you using and which version? I just took your code and added a little extra to make it complete: `include "disciplines.vams" module forum35 (a); output a; electrical a; real...

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Is there any way to update the PDB without replacing each part?

: 0 : 0 April 5, 2016, 12:08 pm

Packager fails with the error "The required symbol is not in the Parts Database" when trying to package a recent translated (DC2DX) schematic. The project packaged with just 4 warnings in DC before it...

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Forum Post: RE: Matlab cadence integration setup

: 0 : 0 April 16, 2019, 11:02 am

You pretty much just need to have matlab in your UNIX path. For more info I would go to support.cadence.com and search for "matlab ade xl" and with the category as Articles and App Notes. There is also...

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LVS BOX: Component with Non-identical signal pins

: 0 : 0 May 27, 2015, 2:58 pm

Dear Calibre users, We are receiving a "COMPONENT TYPES WITH NON-IDENTICAL SIGNAL PINS" message during Calibre LVS (attached below) of a Cadence custom flow design using some standard cell abstracts...

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Unbound pin error from Assura LVS after P&R

: 0 : 0 October 25, 2012, 2:38 pm

Hi,When I do Assura LVS on the layout I got from P&R Encounter, the "unbound pins" error appears in the report. As the attached picture shows, the net marked as green color in both schematic and...

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Figures missing in the RF Design Blogs article of "Measuring Fmax for MOS...

: 0 : 0 February 7, 2018, 10:21 am

Hi,I am following the steps in RF Design Blogs article of "Measuring Fmax for MOS Transistors": https://community.cadence.com/cadence_blogs_8/b/rf/posts/measuring-fmax-for-mos-transistorsHowever, the...

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LVS mismatch on calibre: sub! ; drain and source sharing issue?

: 0 : 0 May 17, 2016, 6:15 pm

Hello there,I have made DFF layout in ON semi 0.5um (previous AMI 0.5um) process. The DRC is clean. Now, I am having an issue with LVS in Calibre. (For LVS, I have created netlist from Cadence and...

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