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Calibre PEX Extraction issue

: 0 : 0 November 28, 2012, 12:17 pm

Hi All, I have had no problems with the DRC and LVS. But when I run PEX, the extraction starts and ends with the following error without producing any output netlist....

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Unbound pin error from Assura LVS after P&R

: 0 : 0 October 25, 2012, 2:38 pm

Hi,When I do Assura LVS on the layout I got from P&R Encounter, the "unbound pins" error appears in the report. As the attached picture shows, the net marked as green color in both schematic and...

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Figures missing in the RF Design Blogs article of "Measuring Fmax for MOS...

: 0 : 0 February 7, 2018, 10:21 am

Hi,I am following the steps in RF Design Blogs article of "Measuring Fmax for MOS Transistors": https://community.cadence.com/cadence_blogs_8/b/rf/posts/measuring-fmax-for-mos-transistorsHowever, the...

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Calibre nmLVS with custom plate capacitance. How to ignore cap in schematic?

: 0 : 0 November 16, 2015, 1:40 pm

Hello! I'm a newbie to Calibre nmLVS. In the layout of my cell, I made a custom plate capacitance with 2 metal layers. This capacitance is between an internal node (b) and the output pin (out). In my...

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Calibre LVS extraction with multiple fingers

: 0 : 0 May 23, 2016, 3:02 pm

Hello, I am using Cadence 6.1.6 with Mentor calibre v2015 3_37.23.I have a problem when I do the LVS test: in my schematic, I instancied a nmos transistor (width = 960nm with 3 fingers of 320nm each)....

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soft_bin=allmodels

: 0 : 0 March 25, 2014, 6:43 am

Hello, Can anyone tell me how to turn on soft_bin=allmodels option in the simulator ? I don't see any option in the IC 5.14 ADE > Simulation > Options > Analog. Regards

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Simulation failed, cannot compile ahdl libraries

: 1 : 0 November 2, 2012, 12:08 pm

Hello, I am using the IBM0.18um kit, and so far can simulate stuff without problems.Now that i have added some customizable ESD structures to schematic, then i layed it all out, checked, lvs'ed, no...

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Compatibility between Boardstation & Expedition

: 0 : 0 February 15, 2015, 9:42 pm

We are using Boardstation for our CAD Designs since 1990. We have various modules in different quantities:Falcon Framework, Design Architect, Board Layout, Fablink and Librarian. Presently we are using...

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NC-Verilog simulation error

: 0 : 0 June 6, 2014, 4:22 am

I am new in using ncvlogI have an error when i am trying to simulate simple inverter |ncelab: *E,CUVMUR (./ihnl/cds0/netlist,19|10): instance 'test.top@Inv_1<module>.PM0' of design unit...

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Is there any way to update the PDB without replacing each part?

: 0 : 0 April 5, 2016, 12:08 pm

Packager fails with the error "The required symbol is not in the Parts Database" when trying to package a recent translated (DC2DX) schematic. The project packaged with just 4 warnings in DC before it...

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