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Trending Articles on Electronic Design Automation (EDA)


Variant manager for multiple PCB in one project

Hello,I'm currently using xDX designer VX1.2 and trying to use the variant manager. First of all, I have 5 boards in one project and the variant seems to not allows that.Indeed, when I open the variant...

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xDX Designer - Shortcut Keys to Quickly Open/Close Schematic Tabs

In xDX Designer, there are tabs across the top, one for each schematic sheet.  Are there shortcut keys or a menu option to quickly close all tabs and quickly open all tabs?

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PCB Design Perfection Starts in the CAD Library – Part 5

Component Lead Forms Before we go deeper into the various component families, we need to clarify the component lead forms of today’s component packaging technology and what is going to be eventually...

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Who did you see at the exhibition hall?

Ah, a title with a “who” in it. What or who is it about? Easy answer. It’s all about you.   Everybody who works for a software company, anybody who has anything to do with the sales process in Mentor...

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Integrated flow parts creation when Access Database already created

I am building my first libraries for my first Pads design. I chose to with integrated flow because this is direction that Mentor seems to be taking Pads in the future. I bypassed netlist flow in its...

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LVS mismatch on calibre: sub! ; drain and source sharing issue?

Hello there,I have made DFF layout in ON semi 0.5um (previous AMI 0.5um) process. The DRC is clean. Now, I am having an issue with LVS in Calibre. (For LVS, I have created netlist from Cadence and...

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Tip of the Week: ModelSim PE Student Edition has new url

There is a new url for the ModelSim PE Student Edition:http://www.mentor.com/company/higher_ed/modelsim-student-edition

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LVS mismatch on calibre: sub! ; drain and source sharing issue?

Hello there,I have made DFF layout in ON semi 0.5um (previous AMI 0.5um) process. The DRC is clean. Now, I am having an issue with LVS in Calibre. (For LVS, I have created netlist from Cadence and...

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Where can I report a QuestaSim bug?

I'm new to this community. I would like to report a bug in QuestaSim. Where and how can I do this?My testbench (< 1000 lines of VHDL code) causes a segmentation fault in QuestaSim. Regards   Patrick...

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xDX Designer - Highlighting All Instances of a Net By Selecting Net in Navigator

In xDX Designer, is there a way for me to highlight a net in the Navigator and get it to highlight that net on all schematic sheets that it is on?

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