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Trending Articles on Electronic Design Automation (EDA)


Problems with license server

Hi,we got several licenses and tried to setup a license server with the "Mentor Graphics Installation" and the "LMTOOLS" Software. When we checked the license server status we get the following error...

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Error on generation of Cadence Allegro 15.Xx netlist generated from DX designer

Hi, I have designed the schematics in dx designer. Now I am generating the cadence allegro compatible netlist but I am having below...

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ODB creation Error message in PADS 9.4

When I create ODB I m getting error message saying that " get-112062-Requested netlist does not exist or has no points" Please refer the attached screen shot.Please let me know anybody have that...

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Decoder Cadence ADE Simulation problem

Hello Experts, I was designing a 2x4 decoder for my use in the implementation of FPGA CLB. when i try to simulate the decoder circuit using the cadence ADE i am getting errors as below. I am also...

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Changing bBox of cell using dbTransformBBox/geTransformUserBBox

Hi,I am trying to reduce the bBox of my cell (it has been enlarged and is much larger than my prBoundary) and I have tried the following commands:cv_layout = dbOpenCellViewByType("lib" "cell"...

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Technology Overview:How to Generate XOR rules for GDS and Oasis input databases

How to generate Calibre XOR Rules for Oasis and GDS database Compare Overview: Generating Calibre XOR rules for input databases when the input layers are not known can be time consuming. This video...

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Virtuoso Video Diary: Noise Simulation in Spectre RF Using Improved...

Did you check out the new Pnoise and Hbnoise Choosing Analyses forms in the MMSIM 15.1 and IC6.1.7 /ICADV12.2 releases? These forms have been significantly improved and simplified. The Direct Plot Form...

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Advancing Digital Verification with Dynamic Duo III's Accelerated Computing

In an era where the complexity of chip design is accelerating at an unprecedented rate, Cadence's latest innovation, the Dynamic Duo III, emerges as a beacon of advancement for chip design teams...

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Silvus Achieves Faster Tapeout of Advanced RF-MS Chip with Cadence Managed Cloud

Silvus Technologies announced the successful tapeout and bring-up of an advanced RF-mixed-signal chip leveraging Cadence tools in the managed cloud environment. This powerful IC boasts an impressive 15...

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Cadence Verification IP AppNotes Demonstrate the Use of Trace Files in...

Cadence Verification IP (VIP) provides solutions for verifying compliance and compatibility of protocols. All VIPs include highly configurable and flexible simulation models of all protocol layers,...

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