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Popular Articles on Electronic Design Automation (EDA)


Forum Post: Convert "xxxxxb#b" to "xxxxx"

Where "xxxxx" can be any sub string and "#" can be any number. However "#" would rarely be more than two digits. The two "b" characters that are converted to " " are always "b". An example input string...

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Calibre PEX Extraction issue

Hi All, I have had no problems with the DRC and LVS. But when I run PEX, the  extraction starts and ends with the following error without producing  any output netlist....

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how to use foreach loop in calibre svrf, using tvf::commands?

Hi, I want to use foreach loop in calibre svrf coding. I know that it can be done using tvf.May i Know the syntax to use foreach loop in svrf coding. Thanks,Venkatesh

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Calibre PEX Extraction issue

Hi All, I have had no problems with the DRC and LVS. But when I run PEX, the  extraction starts and ends with the following error without producing  any output netlist....

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Calibre LVS PEX Warnings and Erros

Hi,I am new to IC design using Cadance. I finished my layout and now trying to run LVS and PEX using Cadance. To run Calibre LVS, I first exported the schematic netlist from Export -> CDL_OUT...

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Re: Using Calibre to generate Verilog netlist and SPEF file PrimeTime

Thanks,Still some questions: 1. Should that the SPEF extraction for a standard cell based digital circuit be excuted using gate-level  extraction?2. Can the STA result based on SPEF from Calibre be...

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Unbound pin error from Assura LVS after P&R

Hi,When I do Assura LVS on the layout I got from P&R Encounter, the "unbound pins" error appears in the report. As the attached picture shows, the net marked as green color in both schematic and...

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" *Error* plus: can't handle (nil + nil) " during netlisting in icfb

Hi, When I am running simulation with Spectre under ADE, I am getting many errors saying that "*Error* plus: can't handle (nil + nil)" during netlisting and I couldn't start simulation. Before these...

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NC-Verilog simulation error

 I am new in using ncvlogI have an error when i am trying to simulate simple inverter          |ncelab: *E,CUVMUR (./ihnl/cds0/netlist,19|10): instance 'test.top@Inv_1<module>.PM0' of design unit...

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Set default fan-out for SOIC/QUAD and BGA in PADS ROUTER

Hi All, I have to create a component with SOP family but when doing the fan-out in PADS ROUTER, the Component Properties always set default fan-out for BGA family. SOIC/QUAD is what Iwant to be. Can...

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