Popular Articles on Electronic Design Automation (EDA)
Forum Post: Convert "xxxxxb#b" to "xxxxx"
Where "xxxxx" can be any sub string and "#" can be any number. However "#" would rarely be more than two digits. The two "b" characters that are converted to " " are always "b". An example input string...
View ArticleCalibre LVS extraction with multiple fingers
Hello, I am using Cadence 6.1.6 with Mentor calibre v2015 3_37.23.I have a problem when I do the LVS test: in my schematic, I instancied a nmos transistor (width = 960nm with 3 fingers of 320nm each)....
View ArticleForum Post: RE: ERROR: Netlister: unable to descend into any of the views...
Hi Andrew, This is the below error I have encountered while running ADE simulation. ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'spectre cmos_sch cmos.sch...
View ArticleForum Post: RE: How to read a text file in a VerilogA code
Which simulator are you using and which version? I just took your code and added a little extra to make it complete: `include "disciplines.vams" module forum35 (a); output a; electrical a; real...
View ArticleForum Post: RE: Matlab cadence integration setup
You pretty much just need to have matlab in your UNIX path. For more info I would go to support.cadence.com and search for "matlab ade xl" and with the category as Articles and App Notes. There is also...
View ArticleIs there any way to update the PDB without replacing each part?
Packager fails with the error "The required symbol is not in the Parts Database" when trying to package a recent translated (DC2DX) schematic. The project packaged with just 4 warnings in DC before it...
View ArticleRe: Using Calibre to generate Verilog netlist and SPEF file PrimeTime
Thanks,Still some questions: 1. Should that the SPEF extraction for a standard cell based digital circuit be excuted using gate-level extraction?2. Can the STA result based on SPEF from Calibre be...
View ArticleUnbound pin error from Assura LVS after P&R
Hi,When I do Assura LVS on the layout I got from P&R Encounter, the "unbound pins" error appears in the report. As the attached picture shows, the net marked as green color in both schematic and...
View ArticleSet default fan-out for SOIC/QUAD and BGA in PADS ROUTER
Hi All, I have to create a component with SOP family but when doing the fan-out in PADS ROUTER, the Component Properties always set default fan-out for BGA family. SOIC/QUAD is what Iwant to be. Can...
View ArticleMicrotec C compiler version 5.0
Dear, Please can anyone guide me or provide subject Software required for compilation of C program.
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