Latest Articles on Electronic Design Automation (EDA)
Forum Post: RE: Implementation of a LTSpice diode model in Cadence
Dear Andrew, A sincere thank you for "watching over my shoulder" and correcting my comment concerning the use of the ".scs" file extension for the PSPICE component netlist file. I, too, and continuing...
View ArticleIC Packagers: More Reasons to Move to 17.4 HotFix 013
As promised, we’re back with some more of the big improvements that are part of the QIR2 update release of 17.4 (HotFix 013). This time, everything is specific to our Allegro® Package Designer Plus...
View ArticleForum Post: Cadence PCB Editor 17.4 will not open SolidWorks DXF as Design...
Hey everyone, I am trying to use the DXF generated from SolidWorks as board geometry design outline but the PCB editor throws errors and won\t accept the DXF file! In contrary, if I try exporting the...
View ArticleOfftopic: How to Make Spatchcock Chicken Under a Brick
It's Martin Luther King Day on Monday. Cadence is off. Breakfast Bytes will not appear. And, as is traditional, I go completely off-topic the day before a break. In the past, a lot of novelty in eating...
View ArticleBoardSurfers: How to Add Fanouts Using Standard Via Structures
An increase in design complexity has forced designers to take novel approaches to meet routing challenges. Long back, designers used to group objects (vias, clines, or shapes) and copy-paste them in...
View ArticleBoardSurfers: How to Add Fanouts Using Standard Via Structures
An increase in design complexity has forced designers to take novel approaches to meet routing challenges. Long back, designers used to group objects (vias, clines, or shapes) and copy-paste them in...
View ArticleEvent: Eliminate Schematic Design Errors with Automated Verification
Detect critical design errors and eliminate design re-spins caused by schematic errors by automating the process of board-level verification.
View ArticleEvent: Eliminate Schematic Design Errors with Automated Verification
Detect critical design errors and eliminate design re-spins caused by schematic errors by automating the process of board-level verification.
View ArticleEvent: SPIE
Attend the Advanced Lithography Digital Forum, the leading event for the lithography community and where leaders come to solve challenges in optical and EUV lithography, patterning technologies,...
View ArticleEvent: SPIE
Attend the Advanced Lithography Digital Forum, the leading event for the lithography community and where leaders come to solve challenges in optical and EUV lithography, patterning technologies,...
View ArticlePopular Articles on Electronic Design Automation (EDA)
Virtuoso: 新序曲-新视角下的拥塞分析
总结: 敬请关注这种独特的布线功能集以及ICADVM 18.1中即将推出的Design Planner工具,并以全新的视角来体验新的拥塞分析辅助工具。(read more)
View ArticleBad component subtype error
Hi,I am using a varactor from a foundry and I get this error while LVS: bad component subtype. I used a single device in schematic & layout to ensure everything is perfect.The report is attached.
View ArticleVideo about C++ structures and classes
My latest video blog is now available. This time I am looking at structures and classes in C++ and considering how they differ. You can see the video here or here: Future video blogs will continue to...
View ArticleleCreatePath net name question
Hi,I was wondering if there was an easy way to attach a name to a net when using the leCreatePath() function. Or does this have to be done separately outside of the function call?Thanks,Elizabeth
View ArticleError when importing outputs into ADE-XL using OCEAN
Hi,I'm trying to import some expressions into ADE-XL test environment using OCEAN. I created a SKILL file (foo.il) with the following: session1 = axlCreateSession("foo") handle1 =...
View ArticleNC-Verilog simulation error
I am new in using ncvlogI have an error when i am trying to simulate simple inverter |ncelab: *E,CUVMUR (./ihnl/cds0/netlist,19|10): instance '[email protected]_1<module>.PM0' of design unit...
View Article昨年のCadence AWRソフトウェアの日本語ウェビナー集を公開
AWRソフトウェアは、高周波設計のソリューションを紹介するために定期的にウェビナーを開催しています。次の2020年のウェビナーがAWRソフトウェアWebinarにまとめられました。 2020年度に公開されたウェビナー Allegroと連携!お客様のレイアウト検証を効率的にするAWR設計環境 AWRソフトウェアの紹介-高周波の設計・検証を高精度に実現する設計環境 AWR...
View ArticleVirtuoso Video Diary: Introducing WSP Manager
Are you an advanced node layout or CAD engineer trying to find a methodology for routing designs in the Virtuoso platform? Interested to learn how to specify tracks for correct-by-construction designs...
View ArticleVirtuoso ICADVM20.1 ISR15 and IC6.1.8 ISR15 Now Available
The IC6.1.8 ISR15 and ICADVM20.1 ISR15 production releases are now available for download.(read more)
View ArticleVeSys 2.0 installation error
Some of my customers have experienced problems installing VeSys 2010_2a. When the installation is almost complete and VeSys manager is started the installation bombs out with the following message:...
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