Latest and Popular Articles on Electronic Design Automation (EDA) |RSSing.com

Latest Articles on Electronic Design Automation (EDA)

Forum Post: RE: OrCAD Capture X 25.1 Professional Stuck on "Initializing MPS"

: 0 : 0 October 24, 2025, 11:08 pm

Hi Jeet After a reboot that problem solved. I still have the "in Allegro, the "search view/pane" always opens no matter how many time i close it,"

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Enhancing PCIe6.0 Performance: Flit Sequence Numbers and Selective NAK Explained

: 0 : 0 October 23, 2025, 5:00 pm

IntroductionThe Flit Sequence Number is a mechanism introduced in the PCIe 6.0 specification, accompanying the transition to Flit Mode operation. This enhancement supersedes the legacy transaction...

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Running Optimized PyTorch Models on Cadence DSPs with ExecuTorch

: 0 : 0 October 22, 2025, 8:00 am

By Vijay Pawar of Cadence and Matthias Cremon of MetaIntroductionDeploying PyTorch models on embedded devices, especially audio DSPs, presents unique challenges. To address these, Cadence and Meta have...

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Sigrity and Systems Analysis 2025.1 Release Now Available

: 0 : 0 October 14, 2025, 12:00 pm

The Sigrity and Systems Analysis (SIGRITY/SYSANLS) 2025.1 release is now available for download at Cadence Downloads. This blog contains important links for accessing this release and introduces some...

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cross coupled oscillator design problem

: 0 : 0 September 21, 2025, 11:27 am

Hello everyone,I'm currently working on the design of a cross-coupled oscillator, based on the circuit architecture shown in the attached figure (from a referenced paper). The resonator has a center...

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cross coupled oscillator design problem

: 0 : 0 September 21, 2025, 11:27 am

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Efficiently Defining the Fundamental, 2nd and 3rd Harmonics Load Impedances

: 0 : 0 September 4, 2025, 12:00 pm

Defining the 2nd and 3rd harmonics load impedances of an RF/microwave transistor in non-linear operation is a strongly determining factor not only for the synthesis of the output matching but also for...

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Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

: 0 : 0 July 31, 2025, 9:00 am

Himax Technologies Inc., a leading supplier and fabless manufacturer of display drivers and other semiconductor products, has successfully deployed Cadence Cerebrus Intelligent Chip Explorer, an...

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LPDDR6: The Next-Generation LPDDR Device Standard and How It Differs from LPDDR5

: 0 : 0 July 30, 2025, 9:36 pm

Low-power DDR SDRAM has been one of the most widely used memories in the semiconductor market today where it’s used in a diverse set of applications that spans mobile/handheld devices, IoT, client and...

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Discover Hidden Gems: Must-See Underrated Cadence Community PCB Design Threads

: 0 : 0 July 23, 2025, 5:32 am

Explore hidden gems in Cadence Community Forums—underrated PCB design threads packed with practical tips, real-world hacks, and expert insights.(read more)

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Forum Post: RE: Convert "xxxxxb#b" to "xxxxx"

: 0 : 0 August 15, 2019, 10:53 am

That works. I need to read up on pcreSubstitute but that's OK. Thanks,

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Forum Post: RE: Import verilog with VDD, VSS, VNW & VPW

: 0 : 0 April 3, 2025, 5:50 am

Hi, what do you mean with " VDD, VSS, VNW & VPW ports are unconnected in the schematic view "? Do you just mean the pin is missing or is any of the impoted cells unconnected? Some general words: -...

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Program: Batch TCL to NSE

: 0 : 0 June 23, 2016, 9:34 am

I was creating TCL scripts to feed into NSE for building symbols. I found that running the code from within the editor took too long, so I wrote them outside in a text file and used this program to...

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VX.2 "Replace Part.." not available

: 0 : 0 October 13, 2016, 7:03 am

I would like to use the Replace functionality in the new version of xDxdesigner VX.2 but If i RMB on symbol there is no option "Replace Part..." as Mentor Videos show. I can see only Replace...

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Clearance between Signals

: 0 : 0 October 10, 2016, 9:42 pm

Hello All , I have a doubt regarding clearance between different single ended signals . Right now we are keeping the same clearance between the traces as that of the signal trace width . For Example ....

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COVER FREE AREA

: 0 : 0 September 27, 2016, 5:33 am

Hi,I merged 5 different gds files into a unique layout like the image for example I would like to know if it's possible to cover all free area around chips with a specific layer, using a command like...

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LVS mismatch on calibre: sub! ; drain and source sharing issue?

: 0 : 0 May 17, 2016, 6:15 pm

Hello there,I have made DFF layout in ON semi 0.5um (previous AMI 0.5um) process. The DRC is clean. Now, I am having an issue with LVS in Calibre. (For LVS, I have created netlist from Cadence and...

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VX.2 "Replace Part.." not available

: 0 : 0 October 13, 2016, 7:03 am

I would like to use the Replace functionality in the new version of xDxdesigner VX.2 but If i RMB on symbol there is no option "Replace Part..." as Mentor Videos show. I can see only Replace...

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Using z-axis clearance rules

: 0 : 0 July 21, 2015, 2:36 pm

If you ever wondered how Z-Axis rules work in the Constraint Manager take a look at this...

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LVS BOX: Component with Non-identical signal pins

: 0 : 0 May 27, 2015, 2:58 pm

Dear Calibre users, We are receiving a "COMPONENT TYPES WITH NON-IDENTICAL SIGNAL PINS" message during Calibre LVS (attached below) of a Cadence custom flow design using some standard cell abstracts...

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