Latest Articles on Electronic Design Automation (EDA)
Forum Post: RE: decompose a component
If you have the source footprint and pad stack files, you can modify the pad stack and update the footprint (Tools->padstack->refresh). If you dont, you can edit the footprint from the board...
View ArticleForum Post: RE: Reading simulation time to a variable
Hi Pedro. It's the first one: "xrun -status -status3". The "-status" tells it to dump a CPU/memory summary at exit, and "-status3" tells it to dump the more verbose version of the summary, with a...
View ArticleForum Post: About Multi technology simulation
I think it can be realized by setting all model files in Model library. What is different from the MTS option? And when I use the MTS option, should I click the button and set Model file one by one to...
View ArticleForum Post: RE: Matlab Error When Starting from Assembler
Hi Andrew, Ahhh, that makes sense. Our CAD group does wrap matlab to submit a bsub job. I'll check the wrapper definition, but that is likely the problem. Thanks Trent
View ArticleForum Post: RE: ADE Explorer Simulation Error
[quote userid="514977" url="~/cadence_technology_forums/f/custom-ic-design/49642/ade-explorer-simulation-error"]Alternatively, run the simulator standalone using the runSimulation file in the netlist\n...
View ArticleForum Post: RE: Detect highlight and optional remove dangling/floating layout
Probably: shapeList=setof(x cvId~>shapes !x->net || !(x->net->instTerms)) Andrew
View ArticleForum Post: RE: How to generate a the full list of all nets in my schematic?
If this is for DE-HDL, here's a great video - Article (20452337) Title: Allegro Design Entry HDL - Creating BOM and Netlist Reports (Video) URL:...
View ArticleWebinar: Simulation of Hydraulic Turbines with Omnis CFD Platform
Join CadenceTECHTALK on December 15! Improving the design of modern turbomachinery requires highly accurate numerical simulations as they contain complex flow features that affect the performance of...
View Article(P)SpiceITUp: Using Curve-Fitting to Optimize a Design
If you are interested in the performance of a circuit that can be best described by a waveform instead of a value, say a practical filter circuit response, curve-fitting is the choice. You can use an...
View ArticlePopular Articles on Electronic Design Automation (EDA)
4K Display Resolution
We use Monitors which habe 4K resolution.Pads Layout is very tiny, several Dialogs are unuseable.Exists there any possible ways to increase Dialogs and Menüs to support 4K Monitors.
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e Language Editing with Emacs
Specman and e have been around for a while, and some clever people have developed a nice syntax highlighting package for Emacs. What does this package do? Well, have a look yourself: Editing in Emacs...
View ArticleRE: How to avoid Hidden State in VerilogA model for SpectreRF
Dear Andrew,I am using AMS kit.I have made circuit using schematic editor but while I am running PSS analysis, it is getting terminated with showing following error: ERROR (SPCRTRF-15177): PSS analysis...
View ArticleForum Post: RE: How to use a custom netlist procedure (and OSSHNL-116 error)
Thanks for the explanation. Can I "create" this shadow database with SKILL so that the netlister will not complain? It doesn't have to make sense because my netlisting function does two things: 1) it...
View ArticleRe: Problems with license server
Hello Ferhat, Please examine your license file and make sure that the host ID on the SERVER line matches that of the machine. Edit the license file like so: replace the string 'put_server_name_here'...
View Article"Unable to open ICDB Connection"
When i am trying to open a Design,I am getting the Following Error "Unable to open ICDB Connection",Any Posible to De bug the Design,Since the ICDB is a Black Box Below is the Error Message in the...
View ArticleFrom Behind the Sofa…
If you are British or are an aficionado of British TV, you will be familiar with the TV series ‘Doctor Who’. If you’re both, and like me, of a certain age, you may recall a childhood of watching this...
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Resetting Your UVM SystemVerilog Environment in the Middle of a Test —...
In general, reset will be applied at different times within a test. 1. Reset at the beginning of a testIn a typical UVM test you might start out by applying a reset, and then go on to configure your...
View ArticleNets Extraction
I have two redundant cores which are synthesised differently. Now after routing i have to extract the similar nets from both cores and find out whether these nets are overlapping or not. As both of the...
View Articleamsspice: *Error: terminated with error code 127
I'm trying to run a RAK, Introduction to AMS Designer SimulationI always get the following error:irun: *E,SPCERR: The program encountered one or more errors while processing the input SPICE file(s) in...
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Forum Post: RE: Parametric simulation in Cadence ADEXL
Dear Andrew, Thank you for your reply can you tell me please why some people perform the parametric sweep from ADEXL not from ADEL, is it because more user friendly or it is more efficient and how ?...
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