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Forum Post: AWR VSS - Discrepancy between Time Domain Simulator & Budget...

Hi, I have an AMP_B block that I'm driving into saturation, and I'm noticing around a 4 dB difference in compressed stage output power depending on if I use the Time Domain Simulator (measured with...

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Forum Post: Frequency Converter Swept Measurements - AWR VSS

Hi, I am trying to obtain frequency-swept Gain and Group Delay plots through a frequency converter modeled in VSS. I have set up a VNA block with the FSTART, FSTOP, FSTEP specified as input (stimulus)...

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Forum Post: Convergence issue related to parametric sweep

The above circuit works fine for me when running the simulation in Pspice until I try to run the simulation as a parametric sweep. Sweeping, for example, c9 results in convergence issues all over my...

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Forum Post: RE: RAVEL documentation?

Great, thanks

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Forum Post: RE: Allowed amount of input wreal data type

i wanted to use the source code option in this forum but it didn't work:)))) sorry I write it again my code below //////////////////////////////////////////////////////////////////////// `include...

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Forum Post: Swap the direction of off-page connectors globally

How to swap the direction of off-page connectors globally? - > To < -

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Sunday Brunch Video for 26th June 2022

https://youtu.be/upd4LIYSez0 Made at embedded world (camera Antti Lautanen) Monday: Public HolidayTuesday: W. Edwards Deming: A Prophet Ignored in His Own LandWednesday: CadenceLIVE: Intel Foundry...

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This Week in CFD - and More

Has it really been since 28 Apr when I last yammered here? That seems to be my most recent blog post, the one in which I introduced you to Fidelity CFD. And that may be the cause of my blogging hiatus...

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AI in Healthcare

Artificial Intelligence and edge computing are revolutionizing the healthcare industry. The recent progress in these technologies is helping medical experts diagnose accurately and quickly.(read more)

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利用 HEMT 和 PHEMT 改善无线通信电路中的增益、速度和噪声

本文要点 高电子迁移率晶体管 (High electron mobility transistors ,HEMT) 和伪高电子迁移率晶体管 (pseudomorphic high electron mobility transistors ,PHEMT) 因其独特的、可提高性能的特点而大受欢迎 在 HEMT 结构中,高电子迁移率是由于掺杂的宽带半导体与未掺杂的窄带隙半导体并列在一起造成的 HEMT...

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Popular Articles on Electronic Design Automation (EDA)


pwrshell failed

I'm having issues with PADSVX.0 licensing. I have the license file of my company (Node-locked, mobile compute), the USB dongle and I've installed both the license and application software. When...

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Forum Post: RE: *ERROR* (DB-320001): Unable to get the Cadence(R) Design...

Dear Andrew, I have the same problems as he does. After changing the kernel file(.cshrc, .bashrc), and I re-run it. Then, I can't access to virtuoso anymore. (btw, I still use ICADV12.3) The terminal...

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Forum Post: Genus - Segmentation Fault

Hello everyone, I am trying to do large-scale Genus RTL synthesis in our new server. But I get Segmentation Fault while doing that. At above you can see the end of my genus.log file. I change...

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Forum Post: RE: Allegro PCB Designer auto-routing

Gridless routing isn't always gridless, Allegro or Expedition. Cadence adheres to the route grid setting unless gloss/centering or using the bubble/hug option for interactive routing.

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Upgrade to PADS Professional

Hi everybody, I wonder why Mentor is talking about 3 PADS packages when PADS Professional is actually not PADS, but an Xpedition light version.Suites are supposed to be “scalable”: PADS Standard/Plus...

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ADE(Analog Design Environment) display problems

Hello,I am using Virtuoso IC6.14 and MMSIM 7.1 or 10.1 version for simulation.But I found the result of the simulation was upside down(Please check the picture).I am currently using CentOS 6.4 for the...

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Clock duty cycle variation with Pnoise?

Hi,From measurements we got a hint that the duty cycles of two clock signals change independently over time. We assume that this is a 1/f-noise effect and thus, I'm looking for a possibility to...

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timeaverage and sample(jitter)

Hi there,I am trying to understand the difference and correlation between timeaveraging and sampled jitter method.For sampling jitter, it calculates noise at particular threshold point. And for time...

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PCB Design Perfection Starts in the CAD Library – Part 17

IPC introduced a new padstack naming convention in the IPC-7351B standard publication and it is used exclusively in the Mentor Graphics LP calculator. This article explains the breakdown of the new...

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When you should wake up and retire your old software.

In an internal meeting at the end of last month I heard a fact announced.  In the total worldwide licenses for Mentor Graphics’ software for Integrated Electrical Systems the balance has changed. There...

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Top-Rated Articles on Electronic Design Automation (EDA)


Forum Post: RE: Translate ConceptHDL to Orcad

Thanks for your comments, I was able to use PCB Librarian Expert yesterday, while the library after translation is not good, I have to move lines/pins to make ti snap to the grid, so I draw new ones by...

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Tom Hausherr's Blog » Padstack

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System Design and Verification

This blog covers topics related to system design and verification including system simulation and analysis, high-level synthesis, acceleration, emulation, HW/SW co-verification, verification IP and...

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