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Forum Post: RE: Issue with impedance matching of differential pair

Just a follow up. You need something like this So this is a diff pair with a Z of 90 Ohms. Layer topology is 2 layers FR4 0.62, ER 4.5. 1/2Oz copper 1.4 mil. Trace to Trace spacing = 6Mil Trace to Top...

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Forum Post: RE: Issue with impedance matching of differential pair

Yes! I am trying to get a controlled impedance of 90 Ohms diff and 45 Ohm single ended on 2 layer stack up

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Sunday Brunch Video for 2nd May 2021

https://youtu.be/1HEd6JCriCQ Made in Groveland CA (camera Carey Guo) Monday: Package Assembly Design KitsTuesday: Rapid Adoption of the Arm Server-Class Processors Wednesday: Arm V9A Thursday:...

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Improve your AppSec program with the Synopsys partner ecosystem

Understand how the Synopsys partner ecosystem can help your organization address your software quality and application security challenges. The post Improve your AppSec program with the Synopsys...

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What Disruptive Changes to Expect from PCI Express Gen 6.0

PCIe (Peripheral Component Interconnect Express) has long been the backbone of complex systems, and provides a high-bandwidth, high-performance link for interconnecting devices imposed by cloud-based...

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What Disruptive Changes to Expect from PCI Express Gen 6.0

PCIe (Peripheral Component Interconnect Express) has long been the backbone of complex systems, and provides a high-bandwidth, high-performance link for interconnecting devices imposed by cloud-based...

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Why automation is critical for your software development

Automation, when done properly, can improve the productivity, quality, safety, and security in your software development. The post Why automation is critical for your software development appeared...

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ASCENT: Finding the Right Parts with Unified Search

Some people say that finding the right components for a design is the most time-consuming part of designing. If that is correct, you need all the help you can get to quickly locate what you need. You...

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ASCENT: Finding the Right Parts with Unified Search

Some people say that finding the right components for a design is the most time-consuming part of designing. If that is correct, you need all the help you can get to quickly locate what you need. You...

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Spectre Tech Tips: Introducing Electrothermal Simulation

Understanding the thermal performance of integrated circuits has been essential to avoid the overheating that can cause circuit malfunctions.  With greater integration, the power dissipation in...

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Popular Articles on Electronic Design Automation (EDA)


Forum Post: Physical verification system menu is not working properly

HI All, Recently physical verification system tool is installed and integrated to virtuoso but the menu options are not working. when i am trying to use any option i am getting the following error...

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Phase Noise Setup doesn't work in port/vsource

I'm simply simulating pss and pnoise for a port/vsource, with added phase noise "freq, noise(dBc)" pairs.In my testbench, there's only the vsource and it's labelled output, and gnd. In ade, I setup pss...

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PutComponent from central library

Is it possible now to add a component from the central library?

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how to open the Paste Map window

when i copy simple 2 resistors with 2 diff pair nets it bring the first resistors t find and i need other resistors but to keep the traces topologyso i need to change it it like it was in 7.9.4 during...

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Forum Post: Verilog IN error

I am importing a synthesized verilog file using the CIW menu File -> Import -> Verilog. The import fails, and the verilogIn.log file displays the following 2 lines only: ERROR (VERILOGIN-540):...

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BoardSurfers: The New 17.4-2019 Dynamic Shape 'Fast' Mode is Truly Fast!

This year, it’s the new Fast shape mode, and I feel like I need to talk about it because it is a game-changer in working with positive shapes when it comes to performance and the display quality of...

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How do I prevent a DRC Net shorting error in PCB design?

  Good Morning,I have a devide that has 4 pins going to the same net, but 1 of those pins is a sense line that goes to another pin on an edge connector... All of the pins are connected together in the...

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Virtuoso Video Diary: Noise Simulation in Spectre RF Using Improved...

Did you check out the new Pnoise and Hbnoise Choosing Analyses forms in the MMSIM 15.1 and IC6.1.7 /ICADV12.2 releases? These forms have been significantly improved and simplified. The Direct Plot Form...

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Automotive threat analysis and risk assessment method

The TARA method provides risk evaluation, assessment, treatment, and planning for identified risks. Learn how to apply this method to the ISO SAE 21434 standard. The post Automotive threat analysis...

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DA_IC Segmentation Fault / Violation

Hi All, I am using ICStudio 2008.1 (yes I realize this is outdated, we have some existing designs and we do not want to make tool changes in the middle of them) running on Linux 64bit. When using da_ic...

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Forum Post: How to define sdc file description for internally generated clock ?

In my design, I have a clock generation block which generate main clock pulse ( no external clock reference is used like PLL ) . I'm facing problem defining sdc clock description. I've tried;...

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Cannot complete a trace with plane flooded

Trying to draw a trace from one pin to another, same net, but it will not complete.  It resists attaching, giving "sketch must end near end of guide" in the output window.  Ctrl+click and selecting...

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Forum Post: ERROR (OSSHNL-109)

Hi, No matter how many times I check and save, every time I try to generate the netlinst I get the below error. Please help me solve this. Cadence Virtuoso version: IC6.1.6.500.1 ERROR (OSSHNL-109):...

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