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Forum Post: RE: Netlister's subcircuit naming convention

Hi Andrew, I met the same issue. It adds "_schematic" to the cell name so the dspf include fail. Could you point me where to find the discussion of " CCR 1592892"?

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Forum Post: RE: Delay and bandwidth calculation for analog signals in Cadence

Dear Famaz, [quote userid="500124" url="~/cadence_technology_forums/f/custom-ic-design/47638/delay-and-bandwidth-calculation-for-analog-signals-in-cadence"] But the problem is that by changing the size...

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Multi-Band Antennas for IoT on the Go — New White Paper

Massive machine type communications (mMTC) along with enhanced Mobile Broadband (eMBB) and Ultra Reliable Low Latency Communications (URLLC) represent the three pillars of the 5G initiative defined by...

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Multi-Band Antennas for IoT on the Go — New White Paper

Massive machine type communications (mMTC) along with enhanced Mobile Broadband (eMBB) and Ultra Reliable Low Latency Communications (URLLC) represent the three pillars of the 5G initiative defined by...

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Boardsurfers: An Introduction to Allegro DesignTrue DFM Rule Aggregator

Design companies often work with multiple PCB fabricators and each fabricator may have a different set of DFM rules. It is a customary practice followed by design companies to create a common...

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Boardsurfers: An Introduction to Allegro DesignTrue DFM Rule Aggregator

Design companies often work with multiple PCB fabricators and each fabricator may have a different set of DFM rules. It is a customary practice followed by design companies to create a common...

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Webinar: Extend the Language Using Specman e Macros!

Using Cadence® Specman® Elite macros lets you extend the e language ─ i.e. invent your own syntax.Today, every verification environment contains multiple macros. Some are simple “syntax sugaring” and...

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Webinar: Extend the Language Using Specman e Macros!

Using Cadence® Specman® Elite macros lets you extend the e language ─ i.e. invent your own syntax.Today, every verification environment contains multiple macros. Some are simple “syntax sugaring” and...

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Spectre Tech Tips: Introducing Spectre XDP-HB (Distributed HB)

Spectre XDP-HB was released in the SPECTRE 20.1 base release as part of the new Spectre X-RF simulation technology. Spectre XDP-HB uses a highly distributed multi-machine multi-core simulation...

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AppSec Decoded: What is driving DevSecOps adoption?

In our latest episode of AppSec Decoded, we explore the main drivers of DevSecOps adoption as noted in the BSIMM11 report. The post AppSec Decoded: What is driving DevSecOps adoption? appeared first...

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Popular Articles on Electronic Design Automation (EDA)


On-demand Web Seminar: Designing and Developing Usable Medical Devices using OSS

This webinar addresses the best practices for user experience (UX) design and application development  for Medical devices running Linux or Android.  Attendees will gain a deeper understanding of the...

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BoardSurfers: The New 17.4-2019 Dynamic Shape 'Fast' Mode is Truly Fast!

This year, it’s the new Fast shape mode, and I feel like I need to talk about it because it is a game-changer in working with positive shapes when it comes to performance and the display quality of...

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How to integrate automated AST tools in your CI/CD pipeline

Selecting AST tools for your CI/CD pipeline requires an understanding of where to integrate and how to configure your tools to get the most out of your investments. The post How to integrate automated...

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How to use variables in Calibre DRC Check Map statement

Hi all, I am very new to Calibre DRC deck creation.For experimentation purposes, I wish to write the statement like this : DRC Check Map myrule GDSII "Smylayer" "$mydtype" "$outputfile" APPEND...

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BoardSurfers: The New 17.4-2019 Dynamic Shape 'Fast' Mode is Truly Fast!

This year, it’s the new Fast shape mode, and I feel like I need to talk about it because it is a game-changer in working with positive shapes when it comes to performance and the display quality of...

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Calibre PEX Extraction issue

Hi All, I have had no problems with the DRC and LVS. But when I run PEX, the  extraction starts and ends with the following error without producing  any output netlist....

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IC Packagers: An Introduction to Off-Grid Degassing

All of you doing advanced node package or silicon interposer substrate design in Allegro® Package Designer know what degassing is. And, while we talked last summer about massive performance...

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ModelSim won't compiles VHDL -> Unexpected signal: 11

Hi Mentor, some Modelsim versions (10.4b, 10.3c and 10.1e) won't completely compile the following VHDL code. Code: library ieee;use ieee.std_logic_1164.all; entity x isgeneric (signal_count         :...

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ISF Simulation using Transient Analysis by injecting Impulse

Hi ,I am trying to get the Impulse Sensitivity function for Ring Oscillator  so I am trying to follow the below steps:i) First I am simulating the oscillator unperturbed and get the unperturbed...

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Tanner EDA - Installation tutorial for Linux Network Client License (Sentinel)

This movie is only for installation of legacy Sentinel versions of Tanner tools.  If you are running more recent FlexNet versions or if you received a TXT license file rather than a TLU license file,...

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