Latest Articles on Electronic Design Automation (EDA)
Forum Post: RE: How to view the output noise curve generated by a certain...
Since the question was about viewing the noise curve from individual devices, a printed noise summary (as suggested by Shawn) doesn't really answer the question. For that you can use the results...
View ArticleForum Post: RE: How to pop-up Log file of ADEXL/ADE Explorer once simulation
Dear Binhngo1210, [quote userid="463441" url="~/cadence_technology_forums/f/custom-ic-design/58499/how-to-pop-up-log-file-of-adexl-ade-explorer-once-simulation"]but when i switch to ADEXL or ADL...
View ArticleForum Post: RE: I need help to write a TCL to change display property...
Hi CadAP, OK I understand there is no method to edit the text justification. I will continue doing it by hand. Thank you for the research.
View ArticleForum Post: Read-Only OA library - creating temporary views
Hello, I have an read only OA library and I would like to create temporary view. There is / was a way how to create a local tmp library and "link" it with read-only one. May I ask you for any...
View ArticleForum Post: RE: DB Doctor download?
Assuming you are using a windows installation, can you please try by going to the windows "run" app and enter "dbdoctor_ui". Hopefully this works. Please let me know what Allegro installation you...
View ArticleForum Post: PASS (schema) Net Custom Property from Schematic to PCB Editor
Hi refer to picture I want to: 1- create a CUSTOM Net property (MyProperty) on a Net of the schematic and then 2- get that property in PCB EDITOR (Allegro Constraint Manager-worksheet = PROPERTIES...
View ArticleForum Post: How to assign different values to various components in Pspice
Hey there! I'm curently working on converting a project from LTspice to Pspice. The problem is that I need to assign different values to a capacitor and resistor depending on the value of a variable...
View ArticleForum Post: How to view the output noise curve generated by a certain device...
Hello, I am simulating output noise current using noise simulation. After simulation, I can plot the output noise in direct plot menu. This curve is the sum of the noise contributed by all devices....
View ArticleForum Post: RE: padstack on symbol
thank u for ur reply. i chekced the color dialog but no black color is assgined on any layers. but i found out that the root cause of the problem, which was a folder name. i used japanese on the...
View ArticlePopular Articles on Electronic Design Automation (EDA)
Catia V6 ixf implementation
Hello all, I'm an harness engineer who is responsible for designing pin to pin schematics (VeSys), 3d harness models (Catia V5), creating manufacturing drawings (Catia V5). From now on we are going to...
View ArticleUsing Calibre to generate Verilog netlist and SPEF file PrimeTime
Hi, I now have a layout containing stadard cells in Cadence Virtuoso, and want to generate a Verilog netlist of this layout and an SPEF file to excute STA for this design using PrimeTime. Can Calibre...
View ArticleCalibre PEX Extraction issue
Hi All, I have had no problems with the DRC and LVS. But when I run PEX, the extraction starts and ends with the following error without producing any output netlist....
View ArticleForum Post: Cadence Virtuoso: Import a large verilog netlist to cadence...
Hello all, I imported a verilog netlist for a layout previously designed in Encounter. When I try to open the schematic and hit check&save, I get these errors: Error: Net "v_CALCULATION_CNTR "...
View ArticleLVS mismatch on calibre: sub! ; drain and source sharing issue?
Hello there,I have made DFF layout in ON semi 0.5um (previous AMI 0.5um) process. The DRC is clean. Now, I am having an issue with LVS in Calibre. (For LVS, I have created netlist from Cadence and...
View Articlelayout filemerge from command line
The following is an example of a script that will merge 2 layout files using the DESIGNrev Tcl batch commands that accept user input. The usage is as follows:$MGC_HOME/bin/calibredrv...
View ArticleWhat do Calibre termination codes mean???
Hello all! I recently updated my PDK, and now everytime I run a DRC or an LVS I get the following message at end of the Calibre Interactive transcript, in red letters: *** Calibre finished with Exit...
View ArticleTechnology Overview:How to Generate XOR rules for GDS and Oasis input databases
How to generate Calibre XOR Rules for Oasis and GDS database Compare Overview: Generating Calibre XOR rules for input databases when the input layers are not known can be time consuming. This video...
View ArticleWelcome to Ask the DxDesigner Expert
Welcome to Ask the DxDesigner Expert, the place for all things DxDesigner! I’m Paolo Spazzini, Product Line Director for PCB Front-End Design. Please feel free to ask whatever questions you’d like,...
View ArticleForum Post: Invalid References - OrCAD Capture
Hello, I have created a schematic in capture and I wanted to split a connector (specifically https://www.digikey.co.uk/product-detail/en/te-connectivity-amp-connectors/1761987-9/A98559TR-ND/1851170 )...
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