Latest and Popular Articles on Electronic Design Automation (EDA) |RSSing.com

Latest Articles on Electronic Design Automation (EDA)

Forum Post: RE: Can we highlight multiple vias by using xy cordinates at a...

: 0 : 0 July 20, 2026, 12:52 pm

If you are manually entering X and Y coordinates, select find filter for vias, right-click and select temp group. At the end of selections, right-click complete.

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Forum Post: Is there a known patch or a specific command-line switch

: 0 : 0 July 20, 2026, 9:06 am

Is there a known patch or a specific command-line switch in Genus Synthesis Solution to prevent the tool from optimization looping during incremental compilation of highly parallelized arithmetic...

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Forum Post: RE: Can we highlight multiple vias by using xy cordinates at a...

: 0 : 0 July 20, 2026, 5:10 am

Hi BC, would you also consider using the Find By Query ui which is found in the Find tab? This ui allows you to select multiple vias using control key selection or shift-key list. We can sort and...

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Forum Post: How to selectively delete advanced degassing holes in Silicon...

: 0 : 0 July 20, 2026, 2:58 am

Here are the steps to selectively delete a few degassing holes/voids in the design: 1. This option is only available with Silicon Layout Option as shown below: 2. Change to the shape application mode...

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Forum Post: Secure Your PCB Intellectual Property with Database Locking in...

: 0 : 0 July 20, 2026, 12:27 am

Collaborating on PCB designs often requires sharing database files with customers, partners, or manufacturing teams. OrCAD X Presto's IP Protection Locking feature helps safeguard sensitive design...

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Forum Post: When should you use LES instead of RANS

: 0 : 0 July 18, 2026, 11:48 pm

For CFD applications, consider using LES (Large Eddy Simulation) when unsteady turbulent structures play a significant role in the engineering problem, rather than focusing solely on the time-averaged...

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Forum Post: RE: Opening project done in Cadence 16.6 with Free version 25.1

: 0 : 0 July 18, 2026, 7:09 am

Regarding the 16.6 project with the .cpm extension you mentioned, I believe it is a schematic project file created via Concept-HDL. Concept-HDL is no longer supported in the latest SPB25.1 release;...

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Forum Post: Cannot Map Schematic Net After Running Quantus QRC

: 0 : 0 July 17, 2026, 6:35 pm

Hello there, I am seeing this warning when I try to probe a node post QRC: *WARNING* (PARA-805) Cannot map schematic net /net31, because the calculated extracted name does not exist in the extracted...

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Forum Post: Can we highlight multiple vias by using xy cordinates at a time...

: 0 : 0 July 17, 2026, 4:07 am

I have a list of vias with its XY locations. I need to highlight all these vias at once. How would I do that in Allegro?

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Forum Post: RE: Opening project done in Cadence 16.6 with Free version 25.1

: 0 : 0 July 17, 2026, 12:26 am

Look like 16.6 project use concepthdl schematic. I am pretty sure it is not supported anymore by 25.1, Cadence "push" a new schematic tool instead (a mix of capture and concept). I guess you have to...

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Forum Post: RE: Convert "xxxxxb#b" to "xxxxx"

: 0 : 0 August 14, 2019, 11:34 pm

Hi MorrisDH , What about this ? procedure(charReplace(str) when(pcreMatchp("(.+)b([0-9]+)b$" str) sprintf(nil "%s " pcreSubstitute("\\1") pcreSubstitute("\\2")) ) )

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Calibre PEX Extraction issue

: 0 : 0 November 28, 2012, 12:17 pm

Hi All, I have had no problems with the DRC and LVS. But when I run PEX, the extraction starts and ends with the following error without producing any output netlist....

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Quick Pin Out - DxDesigner

: 0 : 0 July 24, 2013, 12:16 pm

I had a request for a script in Dx (EE7.9.4) so that the end user could select a symbol in the schematic and run a quick command that would dump into a text file the ref des, part number, pin number,...

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Forum Post: Innovus terminated by internal (SEGV) error/signal...

: 0 : 0 February 5, 2024, 2:35 am

Hello all, I am trying to do a digital implementation flow and trying to run the innovus stylus. But whenever I am trying to initialize the design after reading the RTL netlist, it shows this error...

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Forum Post: Hotfix installation error: SPB 16.6 base release not found

: 0 : 0 January 26, 2017, 7:39 am

Hi, Some time ago I already posted this question: At the moment I've got Cadence Allegro version 16.6 P004 installed and I try to install the hotfix Hotfix_SPB16.60.072. Too bad I got the error: SPB...

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User2User 2008 Automation Workshop - Presentation

: 0 : 0 November 25, 2008, 8:04 am

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AMS simulation using ADE. How to save internal verilog module signals.

: 0 : 0 February 4, 2014, 11:56 am

I am running an AMS simulation using ADE and am having troubling saving some of the signals in my verilog module. I created and imported a .csv file with the list of outputs I wanted to save. However,...

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Forum Post: RE: PLL Phase noise simulation in Cadence Virtuoso

: 0 : 0 March 1, 2020, 1:14 am

Thank you for your time and reply. flicker_noise and white_noise functions are used in phase domain simulations. There is no available VCO code with those functions. All available codes are written...

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Forum Post: Microsoft MS-900 Dumps Tips to Get Results Effortlessly...

: 0 : 0 October 25, 2022, 12:38 am

Here is the Best Way to Overcome All Microsoft MS-900 Exam Preparation Problems The Microsoft 365 Fundamentals MS-900 certification helps you build a career in the IT industry. Success in the...

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