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Latest Articles on Electronic Design Automation (EDA)

Forum Post: RE: Error running Create_Thermal_Flash.il sample from 24.1

: 0 : 0 November 13, 2024, 3:08 am

Hi JS202408156358 I've debugged your code and I believe the issue can be either that the folder /tmp does not exist or that you don't have writing permissions. Let me walk you through what I found out:...

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Forum Post: RE: exporting a modified symbol out

: 0 : 0 November 12, 2024, 10:49 pm

thank u for ur reply, david. is there a way to export the copied data? maybe exporting as a sub-drawing? regards masa

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Forum Post: orcad export netlist not responding

: 0 : 0 November 12, 2024, 7:53 pm

Hi when I export the netlist in capture 17.2 and Allegro Design Entry CIS 17.4. the progress has been running here at netlisting the design and there was no error in the log session. This has been...

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Forum Post: Cross-probe between layout veiw and schematic view

: 0 : 0 November 12, 2024, 2:52 pm

Hi there I am trying to make cross-probe btw layout and schematic view. so when I execute the code in schematic using bindkey, the code will raise the layout view (hiRaiseWindow) and then I want to...

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Forum Post: RE: exporting a modified symbol out

: 0 : 0 November 12, 2024, 10:41 am

Hi Masa, When you load a symbol into allegro/APD it loads the data into a SYMDEF object type, the placed symbols are copies of that data When you modify a symbol in a design layout you are changing the...

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Forum Post: RE: Creating Web/Thermal shape for paste mask

: 0 : 0 November 11, 2024, 1:52 pm

Though, what Hoangkhoi just posted is much simpler and I really like that.

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Forum Post: RE: How to allow hand-made waveform plot into Viva from Assembler?

: 0 : 0 November 11, 2024, 11:31 am

P.S. how can I embed code in a forum post so that it looks neat e.g. as in the example below (taken from here )?

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Forum Post: Allegro PCB Router quit unexpectedly with an exit code of...

: 0 : 0 November 11, 2024, 6:30 am

Has anyone experienced the same situation?

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Forum Post: RE: Force virtuoso (Layout XL) to NOT create warning markers in...

: 0 : 0 November 11, 2024, 3:57 am

Correction.. envSetVal("layoutXL" "incrementalCas" 'boolean nil) to disable incremental check against source.

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Forum Post: RE: Creating Web/Thermal shape for paste mask

: 0 : 0 November 11, 2024, 2:17 am

Hi HoangKhoi, Thanks for sharing your skill routine. It works very well. I'm sure many will find it useful. Best Regards.

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Forum Post: Convert "xxxxxb#b" to "xxxxx"

: 0 : 0 August 14, 2019, 2:26 pm

Where "xxxxx" can be any sub string and "#" can be any number. However "#" would rarely be more than two digits. The two "b" characters that are converted to " " are always "b". An example input string...

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Calibre LVS extraction with multiple fingers

: 0 : 0 May 23, 2016, 3:02 pm

Hello, I am using Cadence 6.1.6 with Mentor calibre v2015 3_37.23.I have a problem when I do the LVS test: in my schematic, I instancied a nmos transistor (width = 960nm with 3 fingers of 320nm each)....

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Forum Post: RE: ERROR: Netlister: unable to descend into any of the views...

: 0 : 0 May 14, 2017, 7:04 pm

Hi Andrew, This is the below error I have encountered while running ADE simulation. ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'spectre cmos_sch cmos.sch...

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Forum Post: RE: How to read a text file in a VerilogA code

: 0 : 0 August 15, 2017, 12:16 am

Which simulator are you using and which version? I just took your code and added a little extra to make it complete: `include "disciplines.vams" module forum35 (a); output a; electrical a; real...

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Is there any way to update the PDB without replacing each part?

: 0 : 0 April 5, 2016, 12:08 pm

Packager fails with the error "The required symbol is not in the Parts Database" when trying to package a recent translated (DC2DX) schematic. The project packaged with just 4 warnings in DC before it...

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Forum Post: RE: Matlab cadence integration setup

: 0 : 0 April 16, 2019, 11:02 am

You pretty much just need to have matlab in your UNIX path. For more info I would go to support.cadence.com and search for "matlab ade xl" and with the category as Articles and App Notes. There is also...

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Set default fan-out for SOIC/QUAD and BGA in PADS ROUTER

: 0 : 0 January 9, 2015, 6:11 pm

Hi All, I have to create a component with SOP family but when doing the fan-out in PADS ROUTER, the Component Properties always set default fan-out for BGA family. SOIC/QUAD is what Iwant to be. Can...

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LVS mismatch on calibre: sub! ; drain and source sharing issue?

: 0 : 0 May 17, 2016, 6:15 pm

Hello there,I have made DFF layout in ON semi 0.5um (previous AMI 0.5um) process. The DRC is clean. Now, I am having an issue with LVS in Calibre. (For LVS, I have created netlist from Cadence and...

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Calibre nmLVS with custom plate capacitance. How to ignore cap in schematic?

: 0 : 0 November 16, 2015, 1:40 pm

Hello! I'm a newbie to Calibre nmLVS. In the layout of my cell, I made a custom plate capacitance with 2 metal layers. This capacitance is between an internal node (b) and the output pin (out). In my...

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nmLVS/PEX: "NO LVS PUSH DEVICES" warning?

: 0 : 0 October 8, 2015, 10:09 am

Hi all! I hope I'm the right place to ask this question. Whenever I do an LVS/PEX I get the following warning in the "Extraction Results" section: "WARNING: Cannot enable LVS PUSH DEVICES because pin...

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