Latest Articles on Electronic Design Automation (EDA)
Forum Post: RE: Using $strobe in Verilog-A module
Thanks Shawn you've pulled the thread some more, all pulling of thread helps! I've discovered that the va compile step actually solves for the derivatives symbolically and I guess stores them away...
View ArticleForum Post: Cooling - End Wall Holes in Autogrid
Hi, I am conducting a numerical simulation of a low speed axial compressor, where I am placing injection holes in the casing of the stator row. I would like to have a high-fidelity simulation, and a...
View ArticleForum Post: RE: Using $strobe in Verilog-A module
Shawn, Thanks for the link, it is rather old but there are some nuggets in that discussion. It will take a little while to go through it carefully. It starts with the question of how to measure...
View ArticleForum Post: RE: Unable to change the environment value of quickalign
Hi Andrew, Thanks for the reply, 1. I need to Toggle the offset in Align Form >>> From User spacing to No spacing, as shown in figure. 2. I am using sub-version ICADVM18.1-64b.500.7 I have...
View ArticleForum Post: setting cell's view in config as dynamic parameter
Hi, I am running a transient sim to verify design performance with ams simulator. The design is complex and clocked block slow down the simulation significantly. I would like to use vams view to...
View ArticleForum Post: RE: Error in my circuit
Your circuit looks fine but the error is due to PSpice lite version which has a node limit. Try upgrading to full version and you should not see this error.
View ArticleForum Post: RE: 50MHz Clock Routing
Hi Melview1. if you mean the characteristic impedance then it will not change however you connect, once the relationship to the reference plane underneath remains consistent. And you have opted for a...
View ArticleForum Post: Error in my circuit
Hi, I'm creating a circuit about to fill and empty a tank. Well, my question is why this circuit creates an error when I simulate it. THANKS!
View ArticleForum Post: Where can I find details of this below attributes?How to instruct...
I was not able to find any documentation (in the tool) to the below attributes: .zero_pin_live_slave_clock_isolation_cell .zero_pin_live_slave_reset_isolation_cell...
View ArticleForum Post: RE: Using $strobe in Verilog-A module
Brad, Because you are running a small-signal analysis (sp), the circuit equations are linearised and it does not step through the code in the Verilog-A model (after the initial DC). It is expected...
View ArticlePopular Articles on Electronic Design Automation (EDA)
Forum Post: RE: Will RHEL 8 work with IC6.1.8
Hi wgtkan IC618 is not officially supported on RHEL8 for now but it should work. You can refer to COS article 20444702 for more details on some of the related issues. Best regards Quek
View ArticleForum Post: RE: Help: ERROR(15053): Can not initialize PSpice UI
Found reason. We used Capture CIS, and "cdssetup" folder is located in somewhere else,E:\CadenceLib\SPB_Data\cdssetup, rather than %HOME%/cdssetup. I copied the original cdssetup folder from my...
View ArticleForum Post: RE: Allegro Design Entry-DRC-Check Power Ground Mismatch Query
Hi oldmouldy, Thanks for your prompt response & clarification.. Below is my case with actual circuit example, but DRC check do not show net has two or more alias..!! For Pin 4 DRC showing, (here i...
View ArticleBest practices for cleaning up Component Library Codes
What are some best practices for combining duplicate or similar Library Codes. For example, we have mistakenly added both color codes 'B' and 'BK' to represent the color Black. Is there a method for...
View ArticleTechnology Overview:How to Generate XOR rules for GDS and Oasis input databases
How to generate Calibre XOR Rules for Oasis and GDS database Compare Overview: Generating Calibre XOR rules for input databases when the input layers are not known can be time consuming. This video...
View ArticleCalibre PEX Extraction issue
Hi All, I have had no problems with the DRC and LVS. But when I run PEX, the extraction starts and ends with the following error without producing any output netlist....
View ArticleImporting CSV connectivity into VeSys 2.0 Harness
DescriptionHarness Manufacturers often develop connectivity in spreadsheet form, or they receive a CSV file containing the connectivity from the OEM (this is usually in the form of a "from-to-list")....
View ArticleVirtuosity: 19 Things I Learned in April 2014 by Browsing Cadence Online Support
Plenty to keep you busy this month. Lots of RAKs, videos, and new Quick Start Guides and FAQs.Application Notes1. Using Annotation Browser with Virtuoso IPVSLearn how to invoke the Annotation Browser...
View ArticleCalibre LVS PEX Warnings and Erros
Hi,I am new to IC design using Cadance. I finished my layout and now trying to run LVS and PEX using Cadance. To run Calibre LVS, I first exported the schematic netlist from Export -> CDL_OUT...
View ArticleCalibre PEX Extraction issue
Hi All, I have had no problems with the DRC and LVS. But when I run PEX, the extraction starts and ends with the following error without producing any output netlist....
View ArticleTop-Rated Articles on Electronic Design Automation (EDA)
Forum Post: RE: Unable to edit a cellview in a RAK
I ran the configuration step again in ISCAPE to solve the first issue. But I still get the above error when trying to NETLIST . The $TMPDIR env variable is not set to anything. Should it be set to...
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