Latest and Popular Articles on Electronic Design Automation (EDA) |RSSing.com"

Latest Articles on Electronic Design Automation (EDA)

Forum Post: RE: Implementation of a LTSpice diode model in Cadence

January 19, 2021, 9:51 am

Dear Andrew, A sincere thank you for "watching over my shoulder" and correcting my comment concerning the use of the ".scs" file extension for the PSPICE component netlist file. I, too, and continuing...

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IC Packagers: More Reasons to Move to 17.4 HotFix 013

January 19, 2021, 6:49 am

As promised, we’re back with some more of the big improvements that are part of the QIR2 update release of 17.4 (HotFix 013). This time, everything is specific to our Allegro® Package Designer Plus...

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Forum Post: Cadence PCB Editor 17.4 will not open SolidWorks DXF as Design...

January 16, 2021, 4:46 pm

Hey everyone, I am trying to use the DXF generated from SolidWorks as board geometry design outline but the PCB editor throws errors and won\t accept the DXF file! In contrary, if I try exporting the...

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Offtopic: How to Make Spatchcock Chicken Under a Brick

January 15, 2021, 5:00 am

It's Martin Luther King Day on Monday. Cadence is off. Breakfast Bytes will not appear. And, as is traditional, I go completely off-topic the day before a break. In the past, a lot of novelty in eating...

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BoardSurfers: How to Add Fanouts Using Standard Via Structures

January 13, 2021, 7:11 am

An increase in design complexity has forced designers to take novel approaches to meet routing challenges. Long back, designers used to group objects (vias, clines, or shapes) and copy-paste them in...

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BoardSurfers: How to Add Fanouts Using Standard Via Structures

January 13, 2021, 7:11 am

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Event: Eliminate Schematic Design Errors with Automated Verification

January 12, 2021, 12:00 am

Detect critical design errors and eliminate design re-spins caused by schematic errors by automating the process of board-level verification.

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Event: Eliminate Schematic Design Errors with Automated Verification

January 12, 2021, 12:00 am

Detect critical design errors and eliminate design re-spins caused by schematic errors by automating the process of board-level verification.

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Event: SPIE

January 12, 2021, 12:00 am

Attend the Advanced Lithography Digital Forum, the leading event for the lithography community and where leaders come to solve challenges in optical and EUV lithography, patterning technologies,...

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Event: SPIE

January 12, 2021, 12:00 am

Attend the Advanced Lithography Digital Forum, the leading event for the lithography community and where leaders come to solve challenges in optical and EUV lithography, patterning technologies,...

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Virtuoso: 新序曲-新视角下的拥塞分析

November 15, 2018, 5:30 am

总结: 敬请关注这种独特的布线功能集以及ICADVM 18.1中即将推出的Design Planner工具，并以全新的视角来体验新的拥塞分析辅助工具。(read more)

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Bad component subtype error

September 17, 2015, 7:06 am

Hi,I am using a varactor from a foundry and I get this error while LVS: bad component subtype. I used a single device in schematic & layout to ensure everything is perfect.The report is attached.

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Video about C++ structures and classes

July 27, 2020, 12:52 am

My latest video blog is now available. This time I am looking at structures and classes in C++ and considering how they differ. You can see the video here or here: Future video blogs will continue to...

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leCreatePath net name question

July 26, 2013, 2:20 pm

Hi,I was wondering if there was an easy way to attach a name to a net when using the leCreatePath() function. Or does this have to be done separately outside of the function call?Thanks,Elizabeth

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Error when importing outputs into ADE-XL using OCEAN

October 30, 2013, 10:01 am

Hi,I'm trying to import some expressions into ADE-XL test environment using OCEAN. I created a SKILL file (foo.il) with the following: session1 = axlCreateSession("foo") handle1 =...

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NC-Verilog simulation error

June 6, 2014, 4:22 am

I am new in using ncvlogI have an error when i am trying to simulate simple inverter |ncelab: *E,CUVMUR (./ihnl/cds0/netlist,19|10): instance '[email protected]_1<module>.PM0' of design unit...

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昨年のCadence AWRソフトウェアの日本語ウェビナー集を公開

January 11, 2021, 5:24 pm

AWRソフトウェアは、高周波設計のソリューションを紹介するために定期的にウェビナーを開催しています。次の2020年のウェビナーがAWRソフトウェアWebinarにまとめられました。 2020年度に公開されたウェビナー Allegroと連携！お客様のレイアウト検証を効率的にするAWR設計環境 AWRソフトウェアの紹介-高周波の設計・検証を高精度に実現する設計環境 AWR...

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Virtuoso Video Diary: Introducing WSP Manager

August 30, 2016, 5:15 pm

Are you an advanced node layout or CAD engineer trying to find a methodology for routing designs in the Virtuoso platform? Interested to learn how to specify tracks for correct-by-construction designs...

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Virtuoso ICADVM20.1 ISR15 and IC6.1.8 ISR15 Now Available

November 23, 2020, 7:52 pm

The IC6.1.8 ISR15 and ICADVM20.1 ISR15 production releases are now available for download.(read more)

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VeSys 2.0 installation error

April 5, 2011, 11:14 pm

Some of my customers have experienced problems installing VeSys 2010_2a. When the installation is almost complete and VeSys manager is started the installation bombs out with the following message:...

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