Latest Articles on Electronic Design Automation (EDA)
Forum Post: RE: OrCAD X Capture CIS : Keyboard shortcut to move a symbol
Hello Sam, The best way to move a part in OrCAD Capture is simply select and drag a component. You can move a part using the below command as well. Select the part which you want to move in schematic....
View ArticleForum Post: How do I create a basic connectivity csv?
First time user of JasperGold. Chip level verif. I want to prove that an arbiter and a buffer are connected. I want to use the connectivity app to do that. I see from the user guide, that I should...
View ArticleForum Post: Setting up host software to interact with firmware in xtensa xplorer
Hi all, I have implemented the firmware simulator for a customized system configuration. Since it's a message queue based firmware, I'm trying to set up a standalone host software to send/process...
View ArticleForum Post: Virtuoso IC6.1.8-64b.500.31 Crashing
After running several heavy simulations through ADE Assembler, the Virtuoso tool occasionally crashes, displaying the "Fatal Application Error". The design is quite large, at about 3GB, so the...
View ArticleCelebrating World Intellectual Property Day
LEGO® is the world’s most famous toy brand. The experience of playing with these toys has endured over the years because of the innumerable possibilities they allow us: from simple textbook models to...
View ArticleForum Post: RE: Auto placer not updating PR boundary
For clarification, I can manually change the PR boundary, but that is not what I want. I want the tool to do it the way the automatic placer did for the layout on the right. It is not easy to do it...
View ArticleForum Post: RE: TCL to change Implementation Type to none for all parts in a...
Hi, this script works to an extent but I had to add the line OrSymbolEditor::execute setLibPartProp {[{"nm":"Implementation","val":""}]} ahead of the line OrSymbolEditor::execute setLibPartProp...
View ArticleForum Post: Topology Workbench Connection Question
Hi Everyone, I am a complete newbie to Sigrity Aurora and have just started learning about it. I am currently in the middle of an online course through the Cadence site and have a question regarding...
View ArticleForum Post: LVS Mismatch
Hello, I added an LVS-cleaned design block at the top level with other blocks and components. At the top level, it is claiming again mismatched instances of the previously LVS cleaned block. It's a...
View ArticlePopular Articles on Electronic Design Automation (EDA)
Tanner EDA - Installation tutorial for Windows Local Node License (Sentinel)
This movie is only for installation of legacy Sentinel versions of Tanner tools. If you are running more recent FlexNet versions or if you received a TXT license file rather than a TLU license file,...
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PCB Design Perfection Starts in the CAD Library – Part 4
SOT (Small Outline Transistor) Components The SOT23 is the most popular of this component family. It has 3, 5, 6 and 8 pin variations and 3 popular pin pitches. 0.50 mm Pitch 0.65 mm Pitch 0.95 mm...
View ArticleCalibre LVS extraction with multiple fingers
Hello, I am using Cadence 6.1.6 with Mentor calibre v2015 3_37.23.I have a problem when I do the LVS test: in my schematic, I instancied a nmos transistor (width = 960nm with 3 fingers of 320nm each)....
View ArticleForum Post: RE: How to use spectre calculator to return x value of a given y?...
There's a CCR to fix this in an IC617 ISR (it may have been fixed now) which is to allow cross to return a value that it doesn't actually cross but exactly reaches. However, as I pointed out in that...
View ArticleForum Post: (Cadence Genus Synthesis) How to use more than one library file...
Below is my Genus synthesis script.tcl, #Script #Setting Library and Design Path set_attribute lib_search_path ../lib/ set_attribute hdl_search_path ../design_files/ #Setting Library and Design Files...
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Metric VS: Imperial Measurement Systems
I’m curious as how do PCB designers route metric pitch BGA’s on a mil grid system or gridless (which consumes memory and CPU)? I can’t figure why anyone would use a mil grid system for any PCB CAD...
View ArticleADE(Analog Design Environment) display problems
Hello,I am using Virtuoso IC6.14 and MMSIM 7.1 or 10.1 version for simulation.But I found the result of the simulation was upside down(Please check the picture).I am currently using CentOS 6.4 for the...
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PCB Design Perfection Starts in the CAD Library – Part 2
Chip Components Smaller Than 1608 (EIA 0603) Before you read this blog ‘Part 2″, read Part 1 White Paper of this series – “PCB Design Perfection Starts in the CAD Library” for the introduction...
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PCB Design Perfection Starts in the CAD Library – Part 5
Component Lead Forms Before we go deeper into the various component families, we need to clarify the component lead forms of today’s component packaging technology and what is going to be eventually...
View ArticleForum Post: RE: Force X in gate level simulation
Hi. You'll need to give us some more detail. Did you pass -ncinitialize to the elaboration command or the simulation one? Did it report any errors, and if so, what errors? Also your subject line...
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View ChannelFPGA-Based Prototyping – Breaking The Three Laws
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