Latest Articles on Electronic Design Automation (EDA)
Forum Post: RE: Copy measurements from one assembler to another
You can export all outputs to a CSV file and import this file from the other maestro view, see...
View ArticleForum Post: ORCAD 17.4 2019 Crash on New Layout
Hey there, I have finished schematics in ORCAD 17.4. Netlists are also created successfully. But when i am creating New layout for new PCB, the ORCAD Hang up at this point. Please provide the remedy...
View ArticleForum Post: RE: Cgg using AC analysis
Dear Elhossiny, [quote userid="514177" url="~/cadence_technology_forums/f/custom-ic-design/48509/cgg-using-ac-analysis"]how to get Cgg using AC analysis[/quote] Is your AC analysis GUI oppoint set to...
View ArticleForum Post: RE: how to get values of sampling points
Dear Holz, [quote userid="505791" url="~/cadence_technology_forums/f/custom-ic-design/48506/how-to-get-values-of-sampling-points/1376958#1376958"]I solve my problem![/quote] Wow - grea! I am very...
View ArticleSunday Brunch Video for 1st August 2021
https://youtu.be/I0AYf5V_irg Made in Long Ridge Open Space Preserve (camera Carey Guo) Monday: HOT CHIPS 2021 PreviewTuesday: Designed with Cadence Video Series Wednesday: July Update Thursday:...
View ArticleThis Week in CFD
It's a Global Recharge Day here at Cadence so why not get recharged by keeping up with the latest news in CFD? For those of you who are readers, there are several good reads this week. (You'll have to...
View ArticleSpectre Tech Tips: Spectre High Impedance Node Check Overview
Circuit checks enable you to analyze typical design problems, such as high impedance nodes, leakage paths between power supplies, timing errors, power issues, connectivity problems, or extreme rise and...
View ArticleSpectre Tech Tips: Spectre High Impedance Node Check Overview
Circuit checks enable you to analyze typical design problems, such as high impedance nodes, leakage paths between power supplies, timing errors, power issues, connectivity problems, or extreme rise and...
View ArticleAppSec Decoded: New executive order changes dynamic of software security...
In this episode of AppSec Decoded, we discuss the impact of the new executive order by the Biden administration on organizations working with the government. The post AppSec Decoded: New executive...
View ArticleSystem Analysis Knowledge Bytes: Computational Fluid Dynamics Roundup – July...
Welcome to the Computational Fluid Dynamics Roundup series, your monthly roundup of the top news and blogs in the CFD domain at Cadence.(read more)
View ArticlePopular Articles on Electronic Design Automation (EDA)
Expedition 9.5 - Can only place a few vias in a conductive pad
Hi, I'm trying to add as many vias into a thermal pad on an IC. I can add about four but then when I try to add more I get an error message "Cannot resolve immovable metal conflicts". I looked at a...
View Articleverify design error
I have been recieving a rather odd error in pads regrading to componets. the error pads give suggest that there is some type of clearange or overlap issue but there is nothing near by and moving the...
View ArticleModelSim won't compiles VHDL -> Unexpected signal: 11
Hi Mentor, some Modelsim versions (10.4b, 10.3c and 10.1e) won't completely compile the following VHDL code. Code: library ieee;use ieee.std_logic_1164.all; entity x isgeneric (signal_count :...
View Article"Unable to open ICDB Connection"
When i am trying to open a Design,I am getting the Following Error "Unable to open ICDB Connection",Any Posible to De bug the Design,Since the ICDB is a Black Box Below is the Error Message in the...
View ArticleHBAC analysis issue, while simulating a mixer from Cadence examples
Hello, I am having two errors in setting up the HBAC analysis. I am trying to run simulations described in Cadence examples/RFworkshop/docs for a mixer.HB analysis runs smoothly, but when I try to run...
View ArticleConvergence error in Transient analysis
Actually i crated a Memristor Model by using VerilogA code. Then i designed logic gates by using the same with different methodology and i got correct simulated output but when i combined all...
View Articleget an error using 3 steps DPI C to simulate systemverilog
Hello all, I want to call a C function within my systemverilog file using DPI C. I have tried the one step (irun -sv hello.c hello.sv )and it worked very well. But the thing I want to do is to create...
View ArticleHOT CHIPS 2021 Preview
As usual in August, it is HOT CHIPS. I always find this one of the most interesting conferences of the year. It gives a lot of insight into the specific products being presented, but also a feel for...
View ArticleSKILL for the Skilled: How to Copy a Hash Table
In this posting I want to look at ways to copy a hash table in SKILL. There are several ways you might naively try to do this, but some of these naive approaches have gotchas which you should be aware...
View ArticleVirtuoso Video Diary: Introducing WSP Manager
Are you an advanced node layout or CAD engineer trying to find a methodology for routing designs in the Virtuoso platform? Interested to learn how to specify tracks for correct-by-construction designs...
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View ChannelTop-Rated Pages on Electronic Design Automation (EDA)
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Cadence Technology Forums
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Paul Johnston's Blog » Design Validation
Somebody surely somewhere has to do some work sometime.
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Cadence Technology Forums
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