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Latest Articles on Electronic Design Automation (EDA)


Forum Post: RE: Virtuoso version update issue

Support for differential (and common-mode) stability analysis using diffstbprobe is available in all sub-versions of IC6.1.8. The interface in ADE changed in a hotfix (I forget which one) but in the...

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Forum Post: xcelium - CSI: *F,INTERR: INTERNAL EXCEPTION

I just completed the setup of xcelium and I am trying to test a very simple vhdl file - I got " CSI: *F,INTERR: INTERNAL EXCEPTION" without any further explanation. Could someone point me to how to...

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Forum Post: RE: Changing Wire Property Name from Port Name to Wire Aliasname

HI karthikeyank , Please use below tcl script to set the schematic net name. Properties are attached to schematic net, you have to iter over schematic net. You can get schematic net from wire. set...

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Forum Post: Split String bit

Hello, I have a Input .meas tran avg isub(xSub_view )from=xTstart to=xTend. The output that I want is .meas tran avg isub(xSub_view )from=xTstart to=xTend .meas tran avg isub(xSub_view )from=xTstart...

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Forum Post: RE: 23.1 CaptureCIS Product Choices

I tested this scenario at my end and below are my findings > On selecting the License as Allegro PCB Design CIS L I have the option to View Database Part for all components. On selecting Allegro X...

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Forum Post: Explorer to run an AMS simulation by copying the files rather...

I know it is possible from ADE Explorer to export simulation scripts for xrun, where we can choose the files to be set as absolute path or copy files. But if we do a run on the Virtuoso ADE Explorer,...

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Forum Post: 23.1 Capture CIS Product Choices

What is the difference between these two: One thing I've noticed is that when choosing "Allegro PCB Design CIS L" I have the option to "View Database Part...": When choosing "Allegro X Designer" that...

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Maximizing Data Center Performance: New Assessment Offering

Running a reliable, cost-efficient, and agile data center is no easy feat, given today's high-performance applications, high-density IT hardware, and emerging carbon emission regulations. These...

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New Hires in Need of Fast Ramp-Up? We Have Ideas

Picture this: Your new hire has completed their mandatory HR training and now needs to ramp up quickly in the tools and technologies that will make them productive. What online courses do you suggest...

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New Hires in Need of Fast Ramp-Up? We Have Ideas

Picture this: Your new hire has completed their mandatory HR training and now needs to ramp up quickly in the tools and technologies that will make them productive. What online courses do you suggest...

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Popular Articles on Electronic Design Automation (EDA)


Tanner EDA - Installation tutorial for Windows Local Node License (Sentinel)

This movie is only for installation of legacy Sentinel versions of Tanner tools.  If you are running more recent FlexNet versions or if you received a TXT license file rather than a TLU license file,...

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How to convert Eagle files to DxDesigner?

Hello all, I am trying to convert some Eagle files( .brd and .sch ) to DxDesigner? I want to modify these files in Mentor Graphics. Is there a method to do this or is it even possible? I was looking...

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Forum Post: Convert "xxxxxb#b" to "xxxxx"

Where "xxxxx" can be any sub string and "#" can be any number. However "#" would rarely be more than two digits. The two "b" characters that are converted to " " are always "b". An example input string...

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Importing CSV connectivity into VeSys 2.0 Harness

DescriptionHarness Manufacturers often develop connectivity in spreadsheet form, or they receive a CSV file containing the connectivity from the OEM (this is usually in the form of a "from-to-list")....

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LVS mismatch on calibre: sub! ; drain and source sharing issue?

Hello there,I have made DFF layout in ON semi 0.5um (previous AMI 0.5um) process. The DRC is clean. Now, I am having an issue with LVS in Calibre. (For LVS, I have created netlist from Cadence and...

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Using Calibre to generate Verilog netlist and SPEF file PrimeTime

Hi, I now have a layout containing stadard cells in Cadence Virtuoso, and want to generate a Verilog netlist of this layout and an SPEF file to excute STA for this design using PrimeTime. Can Calibre...

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LVS BOX: Component with Non-identical signal pins

Dear Calibre users, We are receiving a "COMPONENT TYPES WITH NON-IDENTICAL SIGNAL PINS" message during Calibre LVS (attached below) of a Cadence custom flow design using some standard cell abstracts...

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Tip of the Week: The 'tasklist' and 'findstr' DOS commands

This week we'll explore a couple of very useful commands that you can run in the DOS prompt (cmd.exe) - Tasklist This command lists all of the processes that are running in memory, similar to opening...

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Forum Post: ERROR(ORNET-1113): Bad PSpice net name on part U5

Hello, while simulation in pspice-the error appears- INFO(ORCAP-2191): Creating PSpice Netlist INFO(ORNET-1041): Writing PSpice Flat Netlist D:\dc workspace\orcad\sasa mix...

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Addition of Noise file to input voltage source of Cadence Spetcre

Hi.,      I am facing problem in  adding noise in  transient analysis in cadence spectre .Can help me how to add noise as input source for transient analysis using simulator cadence spectre .

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