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Latest Articles on Electronic Design Automation (EDA)


Forum Post: RE: display description about the commands executed.

thanks!

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Forum Post: RE: Exclude layer interfering with scripted via generation

Sounds great, thanks Andrew. Enjoy your vacation.

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Forum Post: RE: axlUIViewFileCreate not working for html file 17.4

Hi all, I found part of the issue in this thread from EvanShultz : needs to be on the first line of your HTML code. My only issue now is the table borders are missing. Thanks, Jerry

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Forum Post: RE: Getting a signal value using simvision TCL

let's assume no simulator attached, post process. value where the cursor is or a marker will do...

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Forum Post: RE: Getting a signal value using simvision TCL

Are you looking for the current value during a live interactive simulation, or a historic value from an arbitrary point in the waveform (interactive or post-process)?

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Forum Post: RE: Run Monte Carlo with ADE Explorer

The error spells it out pretty clearly. You need to install Xvfb! See The New Virtuoso nograph Server Xvfb was made default Andrew

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Forum Post: Loading simulation results into maestro explorer/assembler

Hi, My simulation setup in explorer/assembler contains lots of calculator expressions for post simulation processing of the results. I had to run a simulation on this setup (that is on the input.scs)...

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CadenceCONNECT: Automated Meshing and Adaptive Remeshing at Bombardier

Pardon the brief post but I've been negligent in keeping you aware of a great example of how Cadence Pointwise Meshing can serve as a framework upon which an entire automated meshing system can be...

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Forum Post: Exclude layer interfering with scripted via generation

I have recently come across some unexpected behavior related to scripted via generation. Specifically, I'm finding that the viaGenerateViasInArea function fails to generate vias in an area in which I...

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Happy Exascale Day!

Did you that the 18th of October each year is celebrated as Exascale Day?  October 18 = 10/18 = 10**18 = 1 quintillion = how many operations an exascale computer can do in a second. By way of...

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Forum Post: RE: how to create panel in orcad 17.4 pcb designer professional

Provided you have OrCAD Pro 17.4 S022. Under manufacture - Fab panelization tool , helps you in panelization. Click on the Help menu once you open Fab tool window to guide you step by step in panel...

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SPECTRE 21.1 Release Now Available

The SPECTRE 21.1 release is now available for download at Cadence Downloads. (read more)

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Forum Post: ADE XL setup not working properly.

Hi. I use IC6.1.7 - I've just setup the software, via installscape, and using my institutions license server. All of that is working. I have a simple schematic that works fine simulating in ADE L ,...

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Virtuoso Video Diary: Knowledge Booster Training Bytes – Part 9 Introduction...

This Blog shows how the Virtuoso Module Generators provide a way to generate multiple Pcell instances into a complex, highly matched, structured array and how you can control the routing style and...

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LVS mismatch on calibre: sub! ; drain and source sharing issue?

Hello there,I have made DFF layout in ON semi 0.5um (previous AMI 0.5um) process. The DRC is clean. Now, I am having an issue with LVS in Calibre. (For LVS, I have created netlist from Cadence and...

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PartQuest Troubleshooting.pdf

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Error plotting finesim psf results with OCEAN/artil

Hi,I have a set of PSF results generated with the finesim simulator (run from ADE through OASIS). Now, I need to run some calculator functions on them.When I open the results directory in OCEAN or...

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How to choose the operating point displayed in IC6.1.6-64b.101 ?

 Hi all,I'm currently use the virtuoso version IC6.1.6-64b.101 and in a previous version I could change and choose which operating point parameter I would to be displayed like Cgs, Region, gm, ... on...

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PSPICE Error Message

I am not a prolific user of Pspice and have just received received a PSice file from an external contractor. The scematic loads ok but when I try to run the file I get the following error message :...

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IC Packagers: Off-the-Shelf Component Support for IC Package Designs

In Allegro® Package Designer Plus prior to the HotFix 019 of release 17.4-2019, any component of type IC in the design shows up in Die-stack Editor. If these are off-the-shelf components, you do not...

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Forum Post: How to solve the problem INFO(ORCAP-2242): Checking Incorrect Pin...

INFO(ORCAP-2242): Checking Incorrect Pin Group Assignment Report for Invalid References Report for Duplicate References -------------------------------------------------- Checking Entire Design:...

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[b]Moderator:[/b] Andrew Beckett.

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