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Forum Post: RE: Measurement function in Allegro Free Physical Viewer

Works well! Thanks a lot.

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Forum Post: OrCAD Allegro 17.4 - PDF Export - Through Hole Pins needs to be...

Hi, How to get all Through hole pins, via, mounting holes filled/solid in exported pdf.. - PDF exported from 17.4 - Looking for something this

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Forum Post: Modifying BSIM-IMG model and using it in Cadence

Hi, I'm trying to modify BSIM-IMG model from Berkley http://bsim.berkeley.edu/models/bsimimg/ for my application (I'm trying to modify the temperature related formulas for Cryo application). I have...

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Virtuoso Video Diary: Knowledge Booster Training Bytes – Part 9 Introduction...

This Blog shows how the Virtuoso Module Generators provide a way to generate multiple Pcell instances into a complex, highly matched, structured array and how you can control the routing style and...

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Forum Post: RE: Measurement function in Allegro Free Physical Viewer

If you are using the new (IMHO brain-dead) 17.4 free viewer, use View>Command & then type in 'show measure' If you are using allegro_free_viewer_classic then it's available as...

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HOT CHIPS: Two Big Beasts

Today, I'm covering two of the biggest chips presented at the recent HOT CHIPS. Ponte Vecchio, Intel's enormous graphics chip intended to be used in Argonne National Laboratories' supercomputer Aurora....

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Pegasus Flies into the GF Technology Summit

Today is the GF Technology Summit, what used to be called GTC in previous years. GF is, of course, GlobalFoundries. We also announced this morning that the Pegasus Verification System has been...

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新しい通信システム解析向けソリューション: Rohde&Schwarz社の標準規格信号を設計で活用

本記事は2021年8月のMicrowave Product Digestに投稿した記事を翻訳したものです。 RF系および部品の設計からCadence VSSおよびRohde&Schwarz VSESIM-VSSソフトウェアを使用した実装まで by Dr.Gent Paparisto and David Vye, Cadence and Markus Loerner, Rohde &...

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I'm Marc Tombroff and This Is How I Mesh

You may be thinking, "He's not Marc Tombroff" and "What's this how I mesh?" First, Marc Tombroff is my new friend and colleague here at Cadence. He was the GM at Numeca prior to their acquisition by...

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ASOC series part 2: How to scale AppSec with application security automation

Learn how ASOC tools make scaling possible through application security automation and orchestration. The post ASOC series part 2: How to scale AppSec with application security automation appeared...

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Popular Articles on Electronic Design Automation (EDA)


Error in Partlister - check locale decimal setting

Dear Sir,I experience error when I doing Partlister in Xpedition VX1It showsError: Value = C1 cant be converted to a fixed type (check locale decimal settings)!Error: Value = C2 cant be converted to a...

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Forum Post: RE: ERROR: Netlister: unable to descend into any of the views...

Dear Andrew, I am using cadence Virtuoso 6.1.5 -64b. I created a verilogA model of a filter using model writer, but when I tried to simulate one of my circuits using the same filter model (verilogA...

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Technology Overview: How to generate CTO file from Calibre Interactive and RVE

Starting from 2013.4 release, user can create CTO file from Calibre RVE and Calibre Interactive. In Interactive, user simply click a check box and CTO file will be generated at the end of Calibre run....

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Forum Post: SV: How to name an unnamed block

If I create a variable in a for-loop: for(int i=0;i<N;i++) begin... It creates and unnamed block. If you $display("%m") in the block it is called "...unmblkX" where is an integer. If I try to name...

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Forum Post: ERROR (ADE-3023)

Hello to everybody, Recently I have begun working with Cadence Virtuoso 6.17. When I want to perform an ADE-L simulation I obtain the following error in the CIW: ERROR (ADE-3023): Cannot run...

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PCB Design Perfection Starts in the CAD Library – Part 5

Component Lead Forms Before we go deeper into the various component families, we need to clarify the component lead forms of today’s component packaging technology and what is going to be eventually...

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Variant manager for multiple PCB in one project

Hello,I'm currently using xDX designer VX1.2 and trying to use the variant manager. First of all, I have 5 boards in one project and the variant seems to not allows that.Indeed, when I open the variant...

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xDX Designer - Shortcut Keys to Quickly Open/Close Schematic Tabs

In xDX Designer, there are tabs across the top, one for each schematic sheet.  Are there shortcut keys or a menu option to quickly close all tabs and quickly open all tabs?

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Modify netlist of a block and resimulate (CDL.... CDF....)

Hello everyone,I am trying to pinpoint a layout error mechanism by modifying the av_extracred view netlist and resimulating the testbench. I have managed to create a manually written netlist as a...

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Get run mode in ADEXL prerun script

I was wondering if it is possible in my ADEXL prerun script to get the run mode of the ADEXL session that started the script.  Basically, I would like to update design varibles if the current run is a...

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Forum Post: RE: How to reduce time needed before transient simulation to be...

You seem very confused by relatively simple things - I suspect you're assigning more meaning to files than maybe they deserve. Let me explain a little about what these "spectre.dc", "spectre.ic" and...

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Tanner EDA - Installation tutorial for Windows Local Node License

OverviewThis movie will show you how to install Tanner Tools on a Windows machine for local node (Mobile Compute) licenses.  DetailsTo install you will need the following items:USB DongleTanner .TLU...

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Tom Hausherr's Blog » library tools

Electronic Component Packages and PCB Libraries

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