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Latest Articles on Electronic Design Automation (EDA)


Forum Post: RE: Capture Hierarchy- using global power pins for signal nets?

I'm considering it because we are using the block diagram primarily to be able to flow the RF flow. If I have to add ports for digital controls it will really clutter the block diagram.

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Forum Post: line to line spacing constraint / drc not working properly

I have line to line spacing set to 0.100. When I slide using hug, the measured gap between the lines is 0.105. If I change the line to line spacing constraint to 0.090 and slide, the measured gap...

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Forum Post: RE: Capture Hierarchy- using global power pins for signal nets?

Off-page connectors carry nets (names) between schematic pages within the same schematic folder. Global Power symbols are used to make power nets globally across the schematic design. Off page...

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Forum Post: RE: Orcad Capture 23.1 won't back annotate from Orcad X / PCB...

No mechanical parts. I did have some mechanical parts on the schematic (just arrows with no pins) but I removed them to see if that would fix the problem - it did not. In one design, I ran the back...

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Forum Post: RE: Older OrCAD schematic viewing. translation error STD.CFG file

Hi, In line 5, PLIB = 'C:\Cadence\PCBViewers_2023\tools\capture\library\*.LIB ' is missing at the end, try adding apostrophe ' in the ending as shown below: PLIB =...

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Forum Post: RE: How to run Celsius Thermal Solver in AWR

Check the following article to know the process: Article (20500399) Title: Microwave Office + Celsius Thermal Simulation with PDK Flow: Part I – Chip Only URL:...

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Forum Post: RE: How to use GetObjectOccurrences of DboPartInst in orcad?

Great! It works! This is my code to puts the occurrences ref out of a Dbo PartInst . set lPartOcc {} set lSelObj [ GetSelectedObjects ] foreach lObj $lSelObj { set lOccCount [ $lObj...

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Forum Post: Changing the number of stdVia arrays with different sizes of vias...

Hi there, I could use any help. Let's say I have 2 or 3 different sizes of via arrays stacked. For example, 1) Group1 : Via1/Via2/Via3 = 0.1umx0.1um 2) Group 2: Via4/Via5 = 0.2umx0.2um 3) Group 3 :...

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Forum Post: Delete layer through hierarchy

Hi all, I need to delete some specific layer through hierarchy. I know I can use Find/Replace and replace those layers to text or unuse layer, but I more prefer to delete them. Do you have any...

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Forum Post: Orcad Capture 23.1 won't back annotate from Orcad X / PCB Designer

I've designed two boards now without too much trouble. The forward annotation works great (ECO | Update PCB). However, the other direction ( ECO | Update Schematic ) always fails. I'm not sure why...

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Forum Post: System task output redirection

Is it possible to redirect the output of a system task, such as stacktrace, to a string in SystemVerilog?

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Forum Post: RE: Quantus QRC (PVS interface) error

I will read the documentation. Thanks for your help.

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PCB Design Perfection Starts in the CAD Library – Part 2

Chip Components Smaller Than 1608 (EIA 0603) Before you read this blog ‘Part 2″, read Part 1 White Paper of this series – “PCB Design Perfection Starts in the CAD Library” for the introduction...

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layout filemerge from command line

The following is an example of a script that will merge 2 layout files using the DESIGNrev Tcl batch commands that accept user input. The usage is as follows:$MGC_HOME/bin/calibredrv...

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LVS mismatch on calibre: sub! ; drain and source sharing issue?

Hello there,I have made DFF layout in ON semi 0.5um (previous AMI 0.5um) process. The DRC is clean. Now, I am having an issue with LVS in Calibre. (For LVS, I have created netlist from Cadence and...

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Problems with license server

Hi,we got several licenses and tried to setup a license server with the "Mentor Graphics Installation" and the "LMTOOLS" Software. When we checked the license server status we get the following error...

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nmLVS/PEX: "NO LVS PUSH DEVICES" warning?

Hi all! I hope I'm the right place to ask this question. Whenever I do an LVS/PEX I get the following warning in the "Extraction Results" section: "WARNING: Cannot enable LVS PUSH DEVICES because pin...

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Forum Post: RE: How to use a custom netlist procedure (and OSSHNL-116 error)

Thanks for the explanation. Can I "create" this shadow database with SKILL so that the netlister will not complain? It doesn't have to make sense because my netlisting function does two things: 1) it...

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Virtuoso Video Diary: Noise Simulation in Spectre RF Using Improved...

Did you check out the new Pnoise and Hbnoise Choosing Analyses forms in the MMSIM 15.1 and IC6.1.7 /ICADV12.2 releases? These forms have been significantly improved and simplified. The Direct Plot Form...

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Technology Overview:How to Generate XOR rules for GDS and Oasis input databases

How to generate Calibre XOR Rules for Oasis and GDS database Compare Overview: Generating Calibre XOR rules for input databases when the input layers are not known can be time consuming. This video...

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Forum Post: Could a trapezoidal ringing be ignorable?

Hi, I have a question about Trapezoidal ringing. During my oscillator simulation, a trapezoidal ringing had happened to an internal node of a three terminal resistor. All terminals of the resistor are...

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