Latest Articles on Electronic Design Automation (EDA)
Forum Post: RE: which SKILL API axl() can get the region information of the...
Hi JuanCR, Thank you for your response. Yes, to be clear, I have identified the segment(dbid) within the region range. I would like to obtain the relevant parameters(Minimum Line Width or DiffPair...
View ArticleForum Post: RE: Set the W/L of an undocked/floated window?
If you're just undocking with the built-in icon on the window, all that will happen is that the first time it will be the size of the docked window. If you then resize it, subsequent undocks will...
View ArticleForum Post: RE: Analysis on the extracted view
Oh, hang-on - I've noticed from your picture above that you've used the Probe Instance (I assume that /I1/MM1/G isn't an instance but a pin). You should have used Probe Terminal (although that still...
View ArticleForum Post: RE: CUSTOM RULE IN ALLEGRO CM TO SUM WIDTH OF MULTILPLE SEGMENTS...
Would it be possible to pour copper shapes in those places?
View ArticleForum Post: CUSTOM RULE IN ALLEGRO CM TO SUM WIDTH OF MULTILPLE SEGMENTS OF...
Hi all, Consider the figure below. The yellow Cline is carrying a certain amount of current. Due to spacing constraints, its width must be reduced. However, multiple, thinner, Clines must be used to...
View ArticleForum Post: RE: Analysis on the extracted view
Does the device on the schematic have a multiplier or multiple fingers? If so, you're only going to end up probing one of the devices (the stb analysis needs either a probe device - iprobe or vsource...
View ArticleForum Post: RE: vManager crashes when analyzing multiple sessions...
Please do not use this forum to get support for tool problems - you need to file a support request at support.cadence.com so that it can be properly tracked through to resolution. All I can really...
View ArticleForum Post: Find Routing problem (Route Vision) and quickly to fix these...
The vision manager is good tool for routing check. but no quickly or effective tool to fix or optimize this problems to be optimized. For example, parallel Gap less than preferred, min seg/Arc...
View ArticleForum Post: RE: skill to create shape based on vias
Here's a more complex alternative: axlCmdRegister("createShapeByVia" 'CreateShapeByVia) defun( CreateShapeByVia () let((visViaSubclasses, subclass, etchLayer, popupAllActive, popupGrayOops, mark,...
View ArticleForum Post: RE: skill to create shape based on vias
I find one bug, show the pic1. big via and small via, the shape is hollow,same as pic1. I want to create shape same as pic2 or pic3.
View ArticlePopular Articles on Electronic Design Automation (EDA)
Tanner EDA - Installation tutorial for Windows Local Node License (Sentinel)
This movie is only for installation of legacy Sentinel versions of Tanner tools. If you are running more recent FlexNet versions or if you received a TXT license file rather than a TLU license file,...
View ArticleTechnology Overview:How to Generate XOR rules for GDS and Oasis input databases
How to generate Calibre XOR Rules for Oasis and GDS database Compare Overview: Generating Calibre XOR rules for input databases when the input layers are not known can be time consuming. This video...
View ArticleRe: Problems with license server
Hello Ferhat, Please examine your license file and make sure that the host ID on the SERVER line matches that of the machine. Edit the license file like so: replace the string 'put_server_name_here'...
View ArticleImporting CSV connectivity into VeSys 2.0 Harness
DescriptionHarness Manufacturers often develop connectivity in spreadsheet form, or they receive a CSV file containing the connectivity from the OEM (this is usually in the form of a "from-to-list")....
View ArticleForum Post: xmvhdl_p: *F,DLUNNE: Can't find STANDARD at...
Hi Team, I am getting the following error while executing a vhd file using XCELIUM1803. Could you please help me to resolve it ? srcs/sample.vhd: xmvhdl_p: *F,DLUNNE: Can't find STANDARD at...
View ArticleNC-Verilog simulation error
I am new in using ncvlogI have an error when i am trying to simulate simple inverter |ncelab: *E,CUVMUR (./ihnl/cds0/netlist,19|10): instance 'test.top@Inv_1<module>.PM0' of design unit...
View ArticleFind cells referenced but undefined in a layout
Use the -undefcells switch in DESIGNrev to list cells referenced but not defined. For instance,>calibredrv -a puts [layout peek design.gds -undefcells]
View ArticleTip of the Week: The 'tasklist' and 'findstr' DOS commands
This week we'll explore a couple of very useful commands that you can run in the DOS prompt (cmd.exe) - Tasklist This command lists all of the processes that are running in memory, similar to opening...
View ArticleForum Post: VHDL-AMS simulation issue
I am using Cadence (ncsim?) to simulate the operation of a MEMS switch. In the code I have a generic time variable (called delay) that acts as step size (highlighted in the code snippet below). I use...
View ArticleRe: DFF: Error: Layer Compare Error
Silkscreen on pads is bad; you can't solder silkscreen. Correcting the decals is best. Most fabs will offer the option to clear the silkscreen from the pads as required.
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