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Latest Articles on Electronic Design Automation (EDA)


Forum Post: RE: Referencing a design variable to another - ADE Assembler

This isn't possible. You can have dependent expressions which reference other variables, but you cannot reference variables in the sweep limits or step (it would lead to an unpredictable set of...

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Forum Post: Pnoise analysis of a clock divider with uneven even/odd cycles

I want to run a pnoise analysis of a clock divider. The output of the divider has uneven even/odd cycles because even edges are derived from the rising edges of its input clock while odd edges are...

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Forum Post: ESD Protection general layout info

Hello I am a new to cadence IC layout and don't quite understand how the thought process works when doing RF ESD layout. Does anyone have a source that gives a general introduction to ESD layout? Thanks

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Forum Post: Adding a polynomial to the GPOLY function

I have the need to create a voltage-controlled current source. I know how to do this from a PSPICE netlist/command line. I'm unfamiliar with the process of adding a polynomial expression to the GPOLY...

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Forum Post: Simulating Noise in OrCAD PSpice

Generally, circuit simulation is performed with ideal conditions. However, every circuit faces noise in its field conditions, which affects its behavior and functionality. Simulating noise by...

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CadenceLIVE Silicon Valley 2022 Preview

CadenceLIVE Silicon Valley is back as an in-person event for 2022, in the Santa Clara Convention Center as usual. The event will take place on Wednesday, June 8 and Thursday, June 9. Vaccination You...

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μWaveRiders:Cadence AWR Design Environment グラフ表示のヒントとコツ

The seventh in the series of AWR Design Environment Tips and Tricks, this blog highlights both common and customized display options for simulation results on a variety of graphs in the AWR Design...

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Successful Thermal Management of 3D-ICs: Accurate, Fast, Efficient and...

Today’s modern electronic designs require ever more functionality and performance to meet consumer demand. These requirements make scaling traditional, flat, 2D-ICs very challenging.  With the recent...

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Leveraging Jasper UNR App for Code Coverage Signoff

Broadcom developed a code coverage signoff flow using Xcelium simulator’s constant propagation, and Jasper UNR App. So, in conclusion about this entire flow and the benefits of unreachability analysis...

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Embedded Vision Summit 2022

Last week was the 11th Embedded Vision Summit. So that means the first one, back in 2011, was just a couple of years after what I regard as the watershed event in vision, the poster session (it didn't...

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Popular Articles on Electronic Design Automation (EDA)


Forum Post: Issue during netlisting-Error(ORNET-1193)

Hi, I am struggling to get a netlist generated. I had to update a schematic that was originally done in an older version. This meant updating issues with footprint names such as removing dashes, dots...

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Re: Calibre LVS extraction with multiple fingers

Hi Sam, I already had this setting, thank you for the help though. Edouard

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Forum Post: RE: Format of "VCD Info File"

Andrew, When I try with real testbench the problem reappears. Here is definition section of .vcd : $scope module tb_top $end $scope module inst_as2005_left $end $scope module ANA $end $var wire 1 !...

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详解时域瞬态分析技术

本文要点: 所有的物理系统在运行动态中都会表现出一些瞬态行为,电子产品也是如此 瞬态分析技术可以帮助了解不同电气状态之间的转换 当检查测量数据或软件仿真数据时,一些基本的瞬态分析技术可用于了解电气状态之间的转换 时域瞬态分析技术在时域中运用,全面展现了不同状态之间的信号转换过程 当打开或关闭 LED...

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amsspice: *Error: terminated with error code 127

I'm trying to run a RAK, Introduction to AMS Designer SimulationI always get the following error:irun: *E,SPCERR: The program encountered one or more errors while processing the input SPICE file(s) in...

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nmLVS/PEX: "NO LVS PUSH DEVICES" warning?

Hi all! I hope I'm the right place to ask this question. Whenever I do an LVS/PEX I get the following warning in the "Extraction Results" section: "WARNING: Cannot enable LVS PUSH DEVICES because pin...

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Importing CSV connectivity into VeSys 2.0 Harness

DescriptionHarness Manufacturers often develop connectivity in spreadsheet form, or they receive a CSV file containing the connectivity from the OEM (this is usually in the form of a "from-to-list")....

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Forum Post: RE: Solved: binary counter in VerilogA with programmable stepsize

Your condition is in the wrong place. It depends what you want of course - in this case I made it so that the output only goes to 0 after the next clock edge by putting the condition inside the @cross...

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what is it PADS-POWERPCB-V10.0-BASIC ? How I can open?

Hi,I have a asc file that I'm not able to open with PADS layout 9.5 ..What do I need to open this file?Thanks

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Vesys 2 - Schematic/Harness Ground connections

Hi. I have a schematic with a ground symbol ('device') connected to a 'splice' and wiring from the splice. This looks great on the schematic but gives a problem with Harness:Problem is I have set up...

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Forum Post: ncelab: *F,OSDINF: instance '[email protected] .I27' of design unit...

Dear all, I have been using ams as simulator for a mixed-signal circuit and it all worked fine. Due to the complexity of my system, I changed the views of digital std cells from schematic to Verilog in...

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Forum Post: I have a problem during import SPICE in Cadence IC 6.1.7

Hello, I tried to import an HSPICE netlist into Cadence IC but I got an error (SPICEIN-24). The netlist I tried to import contained multiple instances of a custom cell that is stored in the same...

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Forum Post: Could a trapezoidal ringing be ignorable?

Hi, I have a question about Trapezoidal ringing. During my oscillator simulation, a trapezoidal ringing had happened to an internal node of a three terminal resistor. All terminals of the resistor are...

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