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回顧CadenceLIVE Taiwan 2021
CadenceLIVE Taiwan 2021熱鬧非凡，活動當天即上千人湧入參與，無論是專題演講、技術分享以及技術論壇，場場人氣爆棚。感謝所有踴躍參與的朋友們，讓Cadence在半導體與電子設計與開發的路上，更向前邁出一大步!今年的CadenceLIVE Taiwan 2021專題演講由Cadence執行長陳立武(Lip-bu Tan)領銜，帶來『推動半導體產業的復興 (Fueling the...
View ArticleForum Post: How to assign net_short property to a shape that is part of a...
Here's what I am doing in order to accomplish this: Obtain component's symbol object, then obtain children of symbol and if child == “shape” then use the following blue line to add NET_SHORT property...
View ArticleForum Post: Can liberate use an encrypted hspice model?
Hi, problem again, can liberate use an encrypted hspice model? thanks in advance!
View ArticleSave the DATE: Design and Test Europe 2022, Antwerp
Design and Test Europe, normally known as just DATE, is back to its usual March schedule for 2022. It will take place from 14th to 23rd March. The plans are for this to be a hybrid event, with the...
View ArticleForum Post: RE: Use if statement to define parameters in Monte Carlo simulation
The simplest would be to use nested ternary expressions like this: parameters \ IFL_value=0 \ ifl=IFL_value<1/4 ? 1 : IFL_value<2/4 ? 2 : IFL_value<3/4 ? 3 : 4 statistics { process{ vary...
View ArticleForum Post: How to interpret area reported by Genus in mm2
I'm a student and new to ASIC design. Kindly let me know the steps I need to follow to interpret Total Area: 554138.039 as reported by Genus, in mm2 . I don't see any units in lib files, although gate...
View ArticleForum Post: RE: Why pin object is converted to shape in Abstract generator
I would suggest contacting customer support . It's quite hard to understand precisely what's going on here, and I think this would be best served by an application engineer being able to see it. Kind...
View ArticleForum Post: Why pin object is converted to shape in Abstract generator
Hi. I have a problem in executing Abstract generator. I want to generate abstract view using Abstract Generator and extract pins. In pin steps, pins are extracted well. But after extract step, pin...
View ArticleForum Post: RE: Matlab interfacing with Virtuoso
It's here: CadenceLIVE Europe 2021 Regards, Andrew
View ArticleForum Post: Create branches between two ports as an array in VerilogA
Hello, I have 1000 branches between the port A and port B. I would like to create the branches as an array (array size = 1000), so that I can use "for" loop inside my VerilogA code of the module....
View ArticlePopular Articles on Electronic Design Automation (EDA)
什么是计算流体力学 (CFD)的 网格划分技术？
本文翻译自Cadence “Breakfast Bytes Blogs”专栏作者Paul McLellan文章“Please Excuse the Mesh: CFD and Pointwise"。 space Cadence 于今年4月收购了流体力学网格划分公司 Pointwise，为了详细了解目前市场领先的计算流体动力学网格生成技术，我们对 Pointwise 的 CEO John...
View ArticleSPECTRE 21.1 Release Now Available
The SPECTRE 21.1 release is now available for download at Cadence Downloads. (read more)
View ArticleLVS mismatch on calibre: sub! ; drain and source sharing issue?
Hello there,I have made DFF layout in ON semi 0.5um (previous AMI 0.5um) process. The DRC is clean. Now, I am having an issue with LVS in Calibre. (For LVS, I have created netlist from Cadence and...
View ArticleForum Post: RE: How to find "file signature" of design files in Cadence...
I should say that in general the files have the ".oa" suffix - but just restoring individual files is unlikely to be useful. CellViews contain a collection of related data, and you need the entire...
View ArticleError when importing outputs into ADE-XL using OCEAN
Hi,I'm trying to import some expressions into ADE-XL test environment using OCEAN. I created a SKILL file (foo.il) with the following: session1 = axlCreateSession("foo") handle1 =...
View ArticleWhite Paper: Ultra-Low Power Memory IPs Using Mentor coolSRAM-6T Technology
The use of embedded static random access memory (eSRAM) in complex ICs has significantly increased in the past three decades. This trend will continue with the growth of ICs designed for rapidly...
View ArticleHow to choose the operating point displayed in IC6.1.6-64b.101 ?
Hi all,I'm currently use the virtuoso version IC6.1.6-64b.101 and in a previous version I could change and choose which operating point parameter I would to be displayed like Cgs, Region, gm, ... on...
View ArticlePSPICE Error Message
I am not a prolific user of Pspice and have just received received a PSice file from an external contractor. The scematic loads ok but when I try to run the file I get the following error message :...
View Article新しい通信システム解析向けソリューション: Rohde＆Schwarz社の標準規格信号を設計で活用
本記事は2021年8月のMicrowave Product Digestに投稿した記事を翻訳したものです。 RF系および部品の設計からCadence VSSおよびRohde＆Schwarz VSESIM-VSSソフトウェアを使用した実装まで by Dr.Gent Paparisto and David Vye, Cadence and Markus Loerner, Rohde &...
View ArticleIC Packagers: Off-the-Shelf Component Support for IC Package Designs
In Allegro® Package Designer Plus prior to the HotFix 019 of release 17.4-2019, any component of type IC in the design shows up in Die-stack Editor. If these are off-the-shelf components, you do not...
View ArticleTop-Rated Articles on Electronic Design Automation (EDA)
Forum Post: How to solve the problem INFO(ORCAP-2242): Checking Incorrect Pin...
INFO(ORCAP-2242): Checking Incorrect Pin Group Assignment Report for Invalid References Report for Duplicate References -------------------------------------------------- Checking Entire Design:...
View ArticleForum Post: ERROR (ADE-3023)
Hello to everybody, Recently I have begun working with Cadence Virtuoso 6.17. When I want to perform an ADE-L simulation I obtain the following error in the CIW: ERROR (ADE-3023): Cannot run...
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Breaking the Three Laws is dedicated to discussing technically challenging ASIC prototyping problems and sharing solutions.
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